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DK-MAXII-1270N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
2–14 Development Kit Version 1.1.0 Altera Corporation
MAX II Development Kit Getting Started User Guide July 2005
Demo Designs
Real-Time ISP Demonstration
MAX II devices provide a feature called real-time ISP. Real-time ISP
allows a device’s Configuration Flash Memory (CFM) to be loaded with
a new design while another design continues to function in the SRAM
(volatile) portion of the device. After a new POF file has been loaded into
the MAX II device with real-time ISP enabled, cycling power causes the
new design to become active in the MAX II device. Further power cycles
simply reload the design residing in the CFM (you cannot switch back
and forth between two different designs).
Using the Demo
w Any two designs will allow for investigation of this feature, with
one important caveat—the design residing in the MAX II device
cannot read from the UFM while the CFM is being overwritten
(while actually programming the device). The example below
holds true whether the designs used are included in this kit or
are custom user designs. Two of the designs included in this kit
continually read from the UFM and thus appear to fail when the
Real-Time ISP option is used and another design is loaded into
the CFM. These two designs are the Vending Machine Demo
and the Functional Test. In order to view the Real-Time ISP
Demo, you should avoid having these designs running in the
MAX II device while loading a second design into the CFM.
However, either of them can be loaded in the CFM while
another design is running.
1. Program the MAX II device with the FunctionalTest.pof file. (Refer
to “Programming the MAX II Device” on page 2–4 for details on
how to load POF files into the MAX II device.)
2. Observe the design functioning as explained in “Running the
Functional Test” on page 2–6.
3. Open the VendingMachineDemo.pof file in the Quartus II
software.
4. Choose Options (Tools menu) and then click Programmer in the list
of options on the left.
5. Check the Enable real-time ISP to allow background
programming check box. See Figure 2–5.
Altera Corporation Development Kit Version 1.1.0 2–15
July 2005 MAX II Development Kit Getting Started User Guide
Getting Started
Figure 2–5. Programmer Options Dialog Box
6. Program the MAX II device with the VendingMachineDemo.pof
file.
7. Observe the Functional Test design still functioning as in step 2.
8. Press S5, which interrupts the V
CCINT
(core voltage) power supply
and forces the MAX II device to reconfigure.
9. Observe the Vending Machine Demo functioning as described
below.
1 Pressing S5 again results in the MAX II device reconfiguring
itself with the Vending Machine Demo. The Functional Test
design is now gone and would have to be reloaded into the CFM
via the Quartus II programmer in order to be loaded into the
MAX II device again.
2–16 Development Kit Version 1.1.0 Altera Corporation
MAX II Development Kit Getting Started User Guide July 2005
Reference Designs
Vending Machine Functionality
After programming the board, you will see the first screen….”Ice Cold
Drinks:”. The available drinks scroll along the bottom of the screen.
S1 resets the board to this first screen
S2 steps through the different screens in sequence:
Screen 1 : Scrolling Drinks
Screen 2 : Make Drink Selection…Press S3 to scroll through drinks
Screen 3 : Deposit funds…………Press S4 to add money
If not enough money has been added, the following message appears
after pressing S2:
“Insufficient $”
“Press S2”
This takes you back to screen 3. When the full amount has been deposited
and S2 is pressed, you come to the final screen:
“Vending Drink”
“Thank You”
Press S1 or S2 to go back to screen 1. Note that the source code for the
Vending Machine Demo is included. This is the only VHDL design that is
included with the kit. It provides an example of the VHDL language for
users new to programmable logic.
Reference
Designs
The MAX II Development Kit provides three reference designs to show
how the MAX II board (and the MAX II device) can interface with other
systems.
Reference Design 1: USB Reference Design
The USB Reference Design provides an example of how to connect a PC
to the MAX II development board using the on-board USB MAC from
Future Technology Devices International (FTDI). The design consists of a
Visual Basic Application and a Quartus II project. Source code for both
projects is included on the MAX II Development Kit CD-ROM. The Verilog
HDL code that makes up the MAX II design contains many explanatory
comments. This design is appropriate for engineers new to
programmable logic (particularly those with software experience) and
provides an excellent starting point for understanding the way in which
programmable logic devices (PLDs) manipulate data. This design was
built such that both the software and hardware portions would be easy to
understand, not for optimum speed or efficiency.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

DK-MAXII-1270N

Mfr. #:
Buy DK-MAXII-1270N
Manufacturer:
Intel / Altera
Description:
Programmable Logic IC Development Tools CPLD Development Kit For EPM1270F256
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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