1/12August 2004
■ HIGH SPEED:
t
PD
=4.7ns (TYP.) at V
CC
= 3.3V
■ 5V TOLERANT INPUTS
■ POWER-DOWN PROTECTION ON INPUTS
■ INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
■ LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
■ LOW NOISE:
V
OLP
= 0.5V (TYP.) at V
CC
=3.3V
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX245 is a low voltage CMOS OCTAL
BUS BUFFER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
This IC is intended for two-way asynchronous
communication between data busses; the
direction of data transmission is determined by
DIR input. The enable input G
can be used to
disable the device so that the busses are
effectively isolated.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z state must
be held HIGH or LOW.
74LVX245
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER
(3-STATE) WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX245MTR
TSSOP 74LVX245TTR
TSSOPSOP
Rev. 5
