FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841602 DATA SHEET
10 REVISION A 4/15/15
FIGURE 4. 841602 SCHEMATIC EXAMPLE
SCHEMATIC EXAMPLE
Figure 4 shows an example of 841602 application schematic. In
this example, the device is operated at V
DD
= 3.3V. The 18pF parallel
resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layout,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of HCSL terminations are shown in this
schematic. The decoupling capacitors should be located as close
as possible to the power pin.
RD1
Not Install
To Logic
Input
pins
C8
.1uf
X1
25MHz
VDD
VDD
BYPASS
RD2
1K
TL3
Zo = 50
To Logic
Input
pins
(U1:24)
R5
50
TL1
Zo = 50
Recommended for PCI
Express Point-to-Point
Connection
RU1
1K
C1
27pF
+
-
REF_SEL
R4 33
Set Logic
Input to
'0'
VDD
R1
10
U1
ICS841602I
1
2
3
4
5
6
7
8
9
10 19
20
21
22
23
24
28
27
26
25
11
12
18
17
13
14
16
15
REF_SEL
REF_IN
VDD
GND
XTAL_IN
XTAL_OUT
MR_nOE
VDD
nc
nc GND
Q0
nQ0
Q1
nQ1
VDD
VDDA
BYPASS
IREF
FSEL
nc
nc
nc
nc
GND
VDD
nc
nc
C5
.1uf
18pF
HCSL Termination
V DD=3.3V
R7
50
C4
0.1u
(U1:8)
VDDA
C7
.1uf
C2
27pF
VDD
Logic Control Input Examples
MR/nOE
RU2
Not Install
VDD
VDD
TL4
Zo = 50
FSEL
C6
.1uf
R6
50
Set Logic
Input to
'1'
C3
10u
R8
50
(U1:3)
R2 33
TL2
Zo = 50
(U1:14)
VDD
VDD
R3
475
VDD
+
-
Recommended for
PCI Express Add-In
Card
VDD
REVISION A 4/15/15
841602 DATA SHEET
11 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
RECOMMENDED TERMINATION
Figure 5A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
FIGURE 5A. RECOMMENDED TERMINATION
Figure 5B is the recommended termination for applications which
require a point to point connection and contain the driver and
FIGURE 5B. RECOMMENDED TERMINATION
receiver on the same PCB. All traces should all be 50Ω impedance.
0.7V Differential HCSL
Clock Driver
0.7V Differential HCSL
Clock Driver
0.7V Differential HCSL
Add-In Card
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841602 DATA SHEET
12 REVISION A 4/15/15
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 841602.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS41602I is the sum of the core power plus the analog plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA
) = 3.465V * (87mA + 15mA) = 353.43mW
Power (outputs)
MAX
= 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 44.5mW = 89mW
Total Power
_MAX
(3.465V, with all outputs switching) = 353.43mW + 89mW = 442.43mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming no air fl ow
and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.442W * 64.5°C/W = 113.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ
JA
FOR 28-PIN TSSOP, FORCED CONVECTION
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 64.5°C/W 60.4°C/W 58.5°C/W

841602AGILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 2 HCSL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
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