REVISION C 11/5/15
843081I-01 DATA SHEET
7 FEMTOCLOCKS
®
CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 843081I-01 pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
CCA
pin. The 10Ω resistor
can also be replaced by a ferrite bead.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
CCA
10μF
.01μF
3.3V or 2.5V
.01μF
V
CC
Figure 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The 843081I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using an 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
ICS843081I-01
0
0
I
I
I-0
I-0
-
-
-
I-0
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1
1
I
I
C
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CS
ICS
CS
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CS
C
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ICS
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CS
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C
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CS
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I
C
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CS
CS
S
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843
843843
843
8
8
843
843
843
4
84
43
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3
843
3
8
8
843
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843
8
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3
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843
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843
84
843
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843
843
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843
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843
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84
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84
43
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84
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8
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843
8
4
4
4
4
4
43
3
3
8
8
8
4
4
4
4
4
3
3
3
8
843
8
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3
3
8
8
8
4
3
8
8
8
8
4
3
3
3
8
8
843
4
43
3
3
081
081
081
081
081
08
0
0
0
8
8
081
081
8
8
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081
08
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081
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081
8
8
8
8
81
81
081
81
0
0
0
081
0
0
0
081
8
8
8
1
1
1
08
0
0
0
08
8
8
08
1
1
1
0
081
0
0
0
0
8
8
08
1
1
1
0
8
8
1
081
0
0
0
0
8
8
8
8
1
1
1
081
0
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1
1
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8
0
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1
8
8
1
081
08
0
0
8
8
8
FEMTOCLOCKS
®
CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
843081I-01 DATA SHEET
8 REVISION C 11/5/15
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed
FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION
to drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
REVISION C 11/5/15
843081I-01 DATA SHEET
9 FEMTOCLOCKS
®
CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50Ω to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in Figure 4C.
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driver
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driver
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-

843081AGI-01LF

Mfr. #:
Manufacturer:
Description:
IC CLK MULTIPLIER LVPECL 8-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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