CAT24C03, CAT24C05
http://onsemi.com
3
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, T
A
= ï40°C to +85°C, unless otherwise specified.)
Symbol
Parameter Conditions Max Units
C
IN
(Note 4)
SDA I/O Pin Capacitance V
IN
= 0 V 8 pF
Input Capacitance (Other Pins) V
IN
= 0 V 6 pF
I
WP
(Note 5) WP Input Current
V
IN
< V
IH
, V
CC
= 5.5 V 200 mA
V
IN
< V
IH
, V
CC
= 3.3 V 150
V
IN
< V
IH
, V
CC
= 1.8 V 100
V
IN
> V
IH
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECïQ100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pullïdown is relatively strong;
therefore the external driver must be able to supply the pullïdown current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pullïdown reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS
(Note 6) (V
CC
= 1.8 V to 5.5 V, T
A
= ï40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Standard Fast
Units
Min Max Min Max
F
SCL
Clock Frequency 100 400 kHz
t
HD:STA
START Condition Hold Time 4 0.6
ms
t
LOW
Low Period of SCL Clock 4.7 1.3
ms
t
HIGH
High Period of SCL Clock 4 0.6
ms
t
SU:STA
START Condition Setup Time 4.7 0.6
ms
t
HD:DAT
Data In Hold Time 0 0
ms
t
SU:DAT
Data In Setup Time 250 100 ns
t
R
SDA and SCL Rise Time 1000 300 ns
t
F
(Note 7) SDA and SCL Fall Time 300 300 ns
t
SU:STO
STOP Condition Setup Time 4 0.6
ms
t
BUF
Bus Free Time Between STOP and START 4.7 1.3
ms
t
AA
SCL Low to Data Out Valid 3.5 0.9
ms
t
DH
Data Out Hold Time 100 100 ns
T
i
(Note 7) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
t
SU:WP
WP Setup Time 0 0
ms
t
HD:WP
WP Hold Time 2.5 2.5
ms
t
WR
Write Cycle Time 5 5 ms
t
PU
(Notes 7, 8) Powerïup to Ready Mode 1 1 ms
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels 0.2 x V
CC
to 0.8 x V
CC
Input Rise and Fall Times v 50 ns
Input Reference Levels 0.3 x V
CC
, 0.7 x V
CC
Output Reference Levels 0.5 x V
CC
Output Load Current Source: I
OL
= 3 mA (V
CC
w 2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
