CY7C419/21/25/29/33
Document #: 38-06001 Rev. *B Page 12 of 25
FIFO is filled to half its capacity plus one word. HF will remain
LOW while less than one half of total memory is available for
writing. The LOW-to-HIGH transition of HF occurs t
RHF
after
the rising edge of R
when the FIFO goes from half full +1 to
half full. HF
is available in standalone and width expansion
modes. FF
goes LOW t
WFF
after the falling edge of W, during
the cycle in which the last available location is filled. Internal
logic prevents overrunning a full FIFO. Writes to a full FIFO are
ignored and the write pointer is not incremented. FF
goes
HIGH tRFF after a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R
initiates a read cycle if the EF is not LOW.
Data outputs (Q
0
–Q
8
) are in a high-impedance condition
between read operations (R
HIGH), when the FIFO is empty,
or when the FIFO is not the active device in the depth
expansion mode.
When one word is in the FIFO, the falling edge of R
initiates a
HIGH-to-LOW transition of EF
. The rising edge of R causes the
data outputs to go to the high-impedance state and remain
such until a write is performed. Reads to an empty FIFO are
ignored and do not increment the read pointer. From the empty
condition, the FIFO can be read t
WEF
after a valid write.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT
) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR
cycle. A LOW pulse on
RT
resets the internal read pointer to the first physical location
of the FIFO. R
and W must both be HIGH while and t
RTR
after
retransmit is LOW. With every read cycle after retransmit,
previously accessed data as well as not previously accessed
data is read and the read pointer is incremented until it is equal
to the write pointer. Full, Half Full, and Empty flags are
governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT
are transmitted also.
Up to the full depth of the FIFO can be repeatedly retrans-
mitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
Expansion In (XI
) and tying First Load (FL) to V
CC
. FIFOs can
be expanded in width to provide word widths greater than nine
in increments of nine. During width expansion mode, all control
line inputs are common to all devices, and flag outputs from
any device can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a MR cycle,
Expansion Out (XO
) of one device is connected to Expansion
In (XI
) of the next device, with XO of the last device connected
to XI
of the first device. In the depth expansion mode the First
Load (FL
) input, when grounded, indicates that this part is the
first to be loaded. All other devices must have this pin HIGH.
To enable the correct FIFO, XO is pulsed LOW when the last
physical location of the previous FIFO is written to and pulsed
LOW again when the last physical location is read. Only one
FIFO is enabled for read and one for write at any given time.
All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created
of word widths in increments of 9. When expanding in depth,
a composite FF
must be created by ORing the FFs together.
Likewise, a composite EF
is created by ORing the EFs
together. HF
and RT functions are not available in depth
expansion mode.
Use of the Empty and Full Flags
In order to achieve the maximum frequency, the flags must be
valid at the beginning of the next cycle. However, because
they can be updated by either edge of the read of write signal,
they must be valid by one-half of a cycle. Cypress FIFOs meet
this requirement; some competitors’ FIFOs do not.
The reason why the flags are required to be valid by the next
cycle is fairly complex. It has to do with the “effective pulse
width violation” phenomenon, which can occur at the full and
empty boundary conditions, if the flags are not properly used.
The empty flag must be used to prevent reading from an empty
FIFO and the full flag must be used to prevent writing into a full
FIFO.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are
ignored by the FIFO, and nothing happens. Next, a single word
is written into the FIFO, with a signal that is asynchronous to
the read signal. The (internal) state machine in the FIFO goes
from empty to empty+1. However, it does this asynchronously
with respect to the read signal, so that it cannot be determined
what the effective pulse width of the read signal is, because
the state machine does not look at the read signal until it goes
to the empty+1 state. In a similar manner, the minimum write
pulse width may be violated by attempting to write into a full
FIFO, and asynchronously performing a read. The empty and
full flags are used to avoid these effective pulse width viola-
tions, but in order to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
