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STLVDS3486 Electrical characteristics
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Note: 1 t
sk(O)
is the maximum delay time difference between the propagation delay of one channel
and that of the others on the same chip with any event on the inputs.
2t
sk(P)
is the magnitude difference in differential propagation delay time between the positive
going edge and the negative going edge of the same channel.
3t
sk(PP)
is the differential channel-to-channel skew of any event between devices. This
specification applies to devices at the same V
CC
, and within 5°C of each other within the
operating temperature range.
Table 6. Switching characteristics
(Over recommended operating conditions unless otherwise noted. All typical values are at
T
A
= 25°C, and V
CC
= 3.3V).
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
PLH
Propagation Delay Time, Low to
High Output
C
L
= 10pF, Fig. 1
1.5 2.5 3.3 ns
t
PHL
Propagation Delay Time, High to
Low Output
1.5 2.5 3.3 ns
t
r
Differential Output Signal Rise
Time
0.4 ns
t
f
Differential Output Signal Fall
Time
0.4 ns
t
sk(O)
Channel to Channel Output Skew
(note1)
0.1 0.3 ns
t
sk(P)
Pulse Skew (|t
PHL
- t
PLH
|) (note2) 0.2 0.4 ns
t
sk(PP)
Part to Part Skew (note3) 1 ns
t
PZH
Propagation Delay Time, High
Impedance to High Level Output
Fig. 2
312ns
t
PZL
Propagation Delay Time, High
Impedance to Low Level Output
512ns
t
PHZ
Propagation Delay Time, High
Level to High Impedance Output
512ns
t
PLZ
Propagation Delay Time, Low
Level to High Impedance Output
512ns
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Test circuit STLVDS3486
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5 Test circuit
Note A: All input pulse are supplied by a generator having the following characteristics:
t
r
or t
f
1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 10 ± 0.2ns.
Note B: C
L
includes instrumentation and fixture capacitance within 6mm of the D.U.T.
Figure 3. Timing test circuit, timing and waveforms
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STLVDS3486 Test circuit
9/15
Note A: All input pulse are supplied by a generator having the following characteristics:
t
r
or t
f
1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 500 ± 10ns.
Note B: C
L
includes instrumentation and fixture capacitance within 6mm of the D.U.T.
Figure 4. Enable and disable time test circuit and waveform
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STLVDS3486BDR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC RECEIVER HS DIFF LINE 16 SOIC
Lifecycle:
New from this manufacturer.
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