DC200A-A

4
DEMO MANUAL DC200
HIGH SPEED ADC
100kHz lowpass filter and works well for frequencies
below 100kHz. At the Nyquist frequency of 200kHz,
the TTE LE1182T-200k-400-720B 200kHz lowpass or
TTE Q70T-200k-30k-400-720B 200kHz bandpass
filters work well. The signal generator and filter should
produce < –96dB THD.
3. Adjust the magnitude of the input signal to within
10mV of negative and positive full scale. This ensures
that the maximum SINAD is achieved without the risk
of overdriving the input and producing unwanted
distortion. The conversion clock frequency can be set
within the range of 0kHz to 400kHz.
4. The conversion results can be observed in several
ways. The onboard LEDs indicate the state of each
QUICK START GUIDE
data bit. This is useful for giving a preliminary indica-
tion that the conversions are taking place and verifying
results when converting DC signals. The 14-bit paral-
lel output data is available on header J6. This allows
monitoring of each bit and can be connected to a logic
analyzer, DSP or oscilloscope. The data format is
two’s complement. Offset binary format is also avail-
able by using D13 instead of D13.
5. Dynamic performance can be measured by using an
FFT-based analyzer. By synchronizing the analog in-
put signal’s frequency to the conversion rate, or using
a windowing function, accurate SINAD, THD or other
dynamic characteristics can be evaluated.
OPERATIO
U
OPERATING THE BOARD
Powering the Board
To use the demo board, apply ±7V to ±15V at 200mA to
the banana jacks J1 and J3, and 0V (GND) to J2. Be careful
to observe the correct polarity. Internal regulators provide
±5V to the LTC1416/LTC1419. An LT1121-5 regulator
(U2) provides 5V for analog and digital circuitry; –5V is
provided for the A/D and buffer by the MC79L05 regulator
(U1).
The Analog Input
The LTC1416/LTC1419 have a unique feature not found on
previous ADCs: differential inputs with good common
mode rejection from DC to over 10MHz. Although this
feature is extremely valuable for rejecting noise and mea-
suring differential signals, the board can also be used to
evaluate the LTC1416/LTC1419 in single-ended mode
(with the “–” input grounded). This board allows evalua-
tion in either mode.
Differential (bipolar) analog signals are applied to the
LTC1416/LTC1419 demo board using BNC connectors J4
(noninverting + input) and J5 (inverting – input). The
analog signal input range is ±2.5V.
The LTC1416/LTC1419 A
IN
+
(noninverting) and A
IN
(inverting) inputs have a common mode range of V
SS
to
V
DD
. The full-scale differential between the signals applied
to A
IN
+
and A
IN
is ±2.5V. For example, when a 1.5V signal
is applied to the A
IN
input, the negative-to-positive full-
scale input range of A
IN
+
is –1V to 4V, corresponding to
an output code of 1000 0000 0000 to 0111 1111 1111.
The demo board is delivered with jumpers JP2 and JP4
closed. This configures the board for a ±2.5V input signal
centered around ground and applied to J4 ( A
IN
+
).
The board includes a recommended lowpass filter (R15
and R16, and C11) across the differential inputs. With the
component values shown, the cutoff frequency (f
S
) is:
1
= 1.56MHz
2π(102)(1000pF)
These values can be altered to meet other circuit and input
signal requirements. For lower bandwidth input signals,
increase the value of C11. For undersampling applications
that take advantage of the input circuitry’s wide band-
width, decrease the capacitance of C11.
The best way to observe the performance of the LTC1416/
LTC1419 is to drive it directly from a low impedance signal
source. However, since some applications involve high
5
DEMO MANUAL DC200
HIGH SPEED ADC
OPERATIO
U
output impedance sources, the board also has provisions
for an onboard LT1363 high speed operational amplifier.
The LT1363, operating as a noninveting buffer, provides
the LTC1416/LTC1419 with a fast settling, low impedance
signal that allows the input voltage to settle fully between
conversions. The buffer is recommended if the source
impedance of the input signal is greater than 930. The
LT1363 demonstrates how to properly drive the LTC1416/
LTC1419. When using the LT1363, open JP2 and close
JP4 and JP3.
Optimum performance is achieved using a signal source
that has low output impedance, is low noise and has low
distortion. Signal generators, such as the B & K Type 1051
Sine Generator, give excellent results. Further, this
generator can be configured to operate referenced to a
master clock signal, as shown in Figure 1.
Applying the Conversion Start Signal
A conversion is initiated by a falling edge on the CONVST
input (BNC J7). The CONVST input uses TTL or CMOS
levels. As shown in Figure 2, CONVST should remain low
until the conversion is completed or returned high within
420ns of the negative going edge, as shown in Figure 3.
During a conversion, transitions on the CONVST input can
cause errors in the D
OUT
output.
Reading the Output Data
The ADC data outputs are buffered by the two 74HC574
latches and are available on connector J6. The latches
drive the LEDs and connector J6. In a practical circuit,
latches are not required unless the ADC is tied to a noisy
data bus. (Refer to the LTC1416 or LTC1419 data sheet for
details on different digital interface modes.)
The output data format of the LTC1416/LTC1419 is two’s
complement. The data can be converted to offset binary by
using D13 instead of D13. Offset binary is used when an
FFT is to be performed on the sampled data. A Data Ready
line (J6, Pin 16) is provided to latch the D
OUT
word. D
OUT
is valid on the rising edge of Data Ready. Two ground lines
are provided on the connector and should be connected to
the receiving system.
The LTC1416/LTC1419 D
OUT
word can be acquired with a
logic analyzer. Conversion data can be stored on a disk and
easily transferred to a PC by using a logic analyzer that has
a PC compatible floppy drive (such as an HP1663A). Once
the data is transfered to a PC, use programs such as
MathCAD or Excel to calculate FFTs. Use the FFTs to obtain
LTC1416/LTC1419 AC specifications, such as signal-to-
noise ratio and total harmonic distortion.
REFERENCE
FREQUENCY
IN
REFERENCE
FREQUENCY
OUT
BRUEL & KJAER
TYPE 1051 SINE
GENERATOR
HEWLETT PACKARD
HP3326A
GENERATOR
HEWLETT PACKARD
HP1663A
LOGIC
ANALYZER
V
IN
CLOCK
LTC1416/
LTC1419
14-BIT A/D
DEMO BOARD
CONVST
DC200 F01
J4
J7
D
OUT
J6
1-14
CLK
Figure 1. Typical Setup for LTC1419 Demo Board
CONVST
BUSY
DATA READY
DC200 F02
Figure 2. Timing Diagram
CONVST
BUSY
DATA READY
>40ns
<420ns
GOOD
DC200 F03
Figure 3. Alternative Timing Diagram
6
DEMO MANUAL DC200
HIGH SPEED ADC
OPERATIO
U
LEDs D0 to D13 provide a visual display of the LTC1416/
LTC1419 digital output word. D0 and D13 display the logic
state of the LSB and MSB, respectively. Remove jumper
JP1 to disable the LEDs, reducing supply consumption up
to 37mA.
Driving CS, RD and SHDN Pins
Jumpers for SHDN, RD and CS (JP5A to JP5C) are shorted
for normal operation. The jumpers can be removed and
these lines externally driven if desired. See the LTC1416 or
LTC1419 data sheet for details on driving these lines.
LAYOUT
A well-designed printed circuit board layout incorporating
the LTC1416/LTC1419 uses separate analog and digital
ground planes. Except for connecting them near U4’s Pin
14, completely isolate the ground planes from each other.
Additionally, they should not overlap if they are on differ-
ent printed circuit board layers. Connecting the LTC1416/
LTC1419 analog (AGND) and digital (DGND) pins to the
analog ground plane ensures the lowest noise operation.
The demonstration board layout (section titled “PCB Lay-
out and Film”) shows the best way to configure and
connect the ground planes. To ensure maximum ground
plane efficiency, especially for the analog ground plane,
it is important to minimize plane-breaking traces.
POWER SUPPLY CONNECTIONS AND BYPASSING
Analog and digital positive supply pins, AV
DD
and DV
DD
respectively, are connected at the device and to the 5V
supply with a single trace. The negative supply pin (V
SS
)
is connected to the –5V supply. The best performance
is achieved by careful attention to proper bypassing.
Bypass AV
DD
and DV
DD
together to the analog ground
plane with a 10µF monolithic ceramic capacitor. Bypass
V
SS
to the analog ground plane with its own 10µF mono-
lithic ceramic capacitor.
The internal voltage reference requires a 22µF monolithic
ceramic capacitor connected between the REFCOMP pin
and the analog ground plane. This bypass capacitor is
necessary because the LTC1416/LTC1419 internal refer-
ence requires a bypass capacitor of at least 1µF for stable
operation. Reference noise can be reduced even further by
using a 1µF monolithic ceramic capacitor connected
between the V
REF
pin and the analog ground plane.
As with all high accuracy, high resolution circuits, the
best performance is achieved by minimizing the lead
lengths of the bypass capacitors.
JUMPER JUMPER NAME JUMPER CONNECTION
JP1 LED Enable Shorting Enables LED Operation. Opening Disables LED Operation
JP2 A
IN
+
Shorted for Unbuffered Operation. Open When Using the Noninverting Input
Buffer. See JP3
JP3 Noninverting Input Buffer Bypass Open for Normal Operation. Short for Buffered Input Signals and Open JP2
JP4 A
IN
Shorted for Single-Ended Operation. Open for Differential Input Signals
JP5A SHDN Shorted for Normal Operation. Open to Externally Drive the SHDN Pin
with a Logic Low for Shutdown Mode or with a Logic High for Normal Operation
JP5B RD Shorted for Normal Operation. Open to Externally Drive the RD Pin
JP5C CS Shorted for Normal Operation. Open to Externally Drive the CS Pin
Table 1. Functional Description of User-Configurable Jumpers

DC200A-A

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Conversion IC Development Tools LTC1419 - 14-Bit, 800ksps ADC
Lifecycle:
New from this manufacturer.
Delivery:
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