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VND830PEP-E
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
VND830
PEP-E
Package
and PC
board t
hermal dat
a
Doc ID 1
0826 Re
v 6
19/25
4
Package and PC b
oard thermal data
4.1
PowerSSO-24 thermal dat
a
Figure 28.
PowerSSO-24 PC board
Note:
Layout c
ondition
of Rth a
nd Zth me
asureme
nts (PCB FR
4 area=
78mm x 78
mm, PC
B
thick
ness=2m
m, Cu th
ickn
ess=35µ
m
, Copper a
reas
: from mi
nimum
pad lay-out
to 8cm
2
).
Figure 29.
R
thj-
am
b
vs PCB copper area in open box
40
45
50
55
60
01
23
45
67
89
RT
Hj
_a
m
b
(
°C
/
W
)
PC
B
C
u he
atsink are
a (cm
^
2)
Obsolete Product(s) - Obsolete Product(s)
Packa
ge and
PC b
oar
d the
rmal
data
VN
D830PE
P-E
20/25
Doc ID 10826
Rev 6
Figure 30.
PowerSSO-24 thermal impedance junct
ion ambient single pulse
Figure 31.
Thermal fitting model of a double channel HSD in PowerSSO-2
4
Equation 1
: pulse cal
culation formula
where
δ
= t
P
/T
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
Ti
me
(
s
)
ZTH
(
°
C
/
W
)
Foot
pri
nt
8 cm
2
Z
TH
δ
R
TH
δ
Z
THtp
1
δ
–
()
+
⋅
=
Obsolete Product(s) - Obsolete Product(s)
VND830
PEP-E
Package
and PC
board t
hermal dat
a
Doc ID 1
0826 Re
v 6
21/25
T
able 16.
Thermal parameter
s
Area/island (cm
2
)
Footprint
8
R1 = R7 (°C/W)
0.1
R2 = R8 (°C/W)
0.9
R3 (°C/W)
1
R4 (°C/W)
4
R5 (°C/W)
13.5
R6 (°C/W)
37
22
C1 = C7 (W
.s
/°C)
0.0006
C2 = C8 (W
.s
/°C)
0.0025
C3 (W
.s/°C)
0.025
C4 (W
.s/°C)
0.08
C5 (W
.s/°C)
0.7
C6 (W
.s/°C)
3
5
Obsolete Product(s) - Obsolete Product(s)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
VND830PEP-E
Mfr. #:
Buy VND830PEP-E
Manufacturer:
STMicroelectronics
Description:
Gate Drivers DOUBLE Ch Hi SIDE DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
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VND830PEP-E
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