MAX7327
I
2
C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
_______________________________________________________________________________________ 7
The four open-drain ports offer latching transition
detection functionality when used as inputs. All input
ports are continuously monitored for changes. An input
change sets 1 of 4 flag bits that identify the changed
input(s). All flags are cleared upon a subsequent read
or write transaction to the MAX7327.
A latching interrupt output INT automatically flags data
changes on any of the I/O ports used as inputs through
an interrupt mask register. Data changes on any input
port forces INT to a logic-low. The interrupt output INT
is deasserted when the MAX7327 is next accessed
through the serial interface.
Internal pullup resistors to V+ are selected by the
address select inputs, AD0 and AD2. Pullups are enabled
on the input ports in groups of two (see Table 2). Use the
slave address selection to ensure that I/O ports used
as inputs are logic-high on power-up. I/O ports with
internal pullups enabled default to a logic-high output
state. I/O ports with internal pullups disabled default to
a logic-low output state.
Output port power-up logic levels are selected by the
address select inputs AD0 and AD2. Ports default to
logic-high or logic-low on power-up in groups of two
(see Tables 2 and 3).
Initial Power-Up
On power-up, the default states of the 12 push-pull out-
put ports and the four open-drain I/O ports are set
according to the I
2
C slave address selection inputs,
AD0 and AD2 (see Tables 2 and 3). For I/O ports used
as inputs, ensure that the default states are logic-high;
therefore, the I/O ports power up in the high-imped-
ance state. All I/O ports configured with pullups
enabled also have a logic-high default state. On power-
up, the transition detection logic is reset, and INT is
deasserted. The transition flags are cleared, indicating
no data changes.
Power-On Reset (POR)
The MAX7327 contains an integral POR circuit that
ensures all registers are reset to a known state on
power-up. When V+ rises above V
POR
(1.6V max), the
POR circuit releases the registers and 2-wire interface
for normal operation. When V+ drops to less than V
POR
,
the MAX7327 resets all register contents to the POR
defaults (Tables 2 and 3).
RST
Input
The active-low RST input operates as a hardware reset
that voids any I
2
C transaction involving the MAX7327,
forcing the MAX7327 into the I
2
C STOP condition. A
reset does not affect the interrupt output (INT).
Standby Mode
When the serial interface is idle, the MAX7327 automat-
ically enters standby mode drawing minimal supply
current.
Slave Address, Power-Up Default Logic
Levels, and Input Pullup Selection
Address inputs AD0 and AD2 determine the MAX7327
slave address and select which inputs have pullup
resistors. Pullups are enabled on the input ports in
groups of two (see Table 2).
The MAX7327 slave address is determined on each I
2
C
transmission, regardless of whether the transmission is
actually addressing the MAX7327. The MAX7327 distin-
guishes whether address inputs AD0 and AD2 are con-
nected to SDA or SCL instead of fixed-logic levels V+
or GND during the transmission. The MAX7327 slave
PART
I
2
C
SLAVE
ADDRESS
INPUTS
INPUT
INTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
CONFIGURATION
MAX7323 110xxxx Up to 4 Up to 4 4
4 I/O, 4 output-only versions:
4 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
4 push-pull outputs with selectable power-up default
levels.
MAX7328
MAX7329
0100xxx
0111xxx
Up to 8 Up to 8
PCF8574-, PCF8574A-compatible versions:
8 open-drain I/O ports with nonlatching transition
detection interrupt and pullups on all ports.
Table 1. MAX7319–MAX7329 Family Comparison (continued)
MAX7327
address can be configured dynamically in the applica-
tion without cycling the device supply.
On initial power-up, the MAX7327 cannot decode the
address inputs AD0 and AD2 fully until the first I
2
C
transmission. AD0 and AD2 initially appear to be con-
nected to V+ or GND. This is important because the
address selection is used to determine the power-up
default states of the output ports, I/O port initial logic
state, and whether pullups are enabled. At power-up,
the I
2
C SDA and SCL bus interface lines are high
impedance at the I/O pins of every device (master or
slave) connected to the bus, including the MAX7327.
This is guaranteed as part of the I
2
C specification.
Therefore, when address inputs AD0 and AD2 are con-
nected to SDA or SCL during power-up, they appear to
be connected to V+. The pullup selection logic uses
AD0 to select whether pullups are enabled for ports P2
and P3, and uses AD2 to select whether pullups are
enabled for ports P4 and P5. The rule is that a logic-
high, SDA, or SCL connection selects the pullups and
sets the logic state to high. A logic-low deselects the
pullups and sets the default logic state to low. The
pullup configuration is correct on power-up for a stan-
dard I
2
C configuration, where SDA or SCL are pulled
up to V+ by the external I
2
C pullup resistors.
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true; for example,
in applications in which there is legitimate bus activity
during power-up. If SDA and SCL are terminated with
pullup resistors to a different supply voltage to the
MAX7327’s supply voltage, and if that pullup supply
rises later than the MAX7327’s supply, then SDA or
SCL may appear at power-up to be connected to GND.
In such applications, use the four address combina-
tions that are selected by connecting address inputs
AD0 and AD2 to V+ or GND (shown in bold in Tables 2
and 3). These selections are guaranteed to be correct
at power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, an
unexpected combination of pullups might be asserted
until the first I
2
C transmission (to any device, not neces-
sarily the MAX7327) is put on the bus.
I
2
C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
8 _______________________________________________________________________________________
PIN
CONNECTION
DEVICE ADDRESS PORTS POWER-UP DEFAULT 40kΩ INPUT PULLUPS ENABLED
AD2 AD0 A6 A5 A4 A3 A2 A1 A0 O7 O6 P5 P4 P3 P2 O1 O0 O7 O6 P5 P4 P3 P2 O1 O0
SCL GND110000011110000 YY
SCL V+ 110000111111111 YYYY
SCL SCL 110001011111111 YYYY
SCL SDA 110001111111111 YYYY
SDAGND110010011110000 YY
SDA V+ 110010111111111 YYYY
SDA SCL 110011011111111 YYYY
SDA SDA 110011111111111 YYYY
GNDGND110100000000000
GND V+ 110100100001111 YY
GND SCL 110101000001111 YY
GNDSDA 110101100001111 YY
V+ GND110110011110000 YY
V+ V+ 110110111111111 YYYY
V+ SCL 110111011111111 YYYY
V+ SDA 110111111111111
Pullups are not enabled for push-pull outputs
YYYY
Pullups are not enabled for push-pull outputs
Table 2. MAX7327 Address Map for Outputs O0, O1, O6, O7, and Ports P2–P5
MAX7327
I
2
C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
_______________________________________________________________________________________ 9
PIN
C O NN EC TIO N
DEVICE ADDRESS OUTPUTS POWER-UP DEFAULT
AD2 AD0 A6 A5 A4 A3 A2 A1 A0 O15 O14 O13 O12 O11 O10 O9 O8
SCLGND101000011110000
SCLV+101000111111111
SCLSCL101001011111111
SCLSDA101001111111111
SDAGND101010011110000
SDAV+101010111111111
SDASCL101011011111111
SDASDA101011111111111
GNDGND101100000000000
GNDV+101100100001111
GNDSCL101101000001111
GNDSDA101101100001111
V+GND101110011110000
V+ V+ 1 0 1110 1 11111111
V+SCL101111011111111
V+SDA101111111111111
Table 3. MAX7327 Address Map for Outputs O8–O15
I/O Port Inputs
I/O port inputs switch at CMOS logic levels as deter-
mined by the expander’s supply voltage, and are over-
voltage tolerant to +6V, independent of the expander’s
supply voltage.
I/O Port Input Transition Detection
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed
through the serial interface. The state of the ports is
stored in an internal “snapshot” register for transition
monitoring. The snapshot is continuously compared
with the actual input conditions, and if a change is
detected for any port input, INT is asserted to signal a
state change. The input ports are sampled (internally
latched into the snapshot register) and the old transi-
tion flags cleared during the I
2
C acknowledge of every
MAX7327 read and write access. The previous port
transition flags are read through the serial interface as
the second byte of a 2-byte read sequence.
A long read sequence (more than 2 bytes) can be used
to poll the expander continuously without the overhead
of resending the slave address. If more than 2 bytes
are read from the expander, the expander repeatedly
returns the 2 bytes of input port data followed by the
transition flags. The inputs are repeatedly resampled
and the transition flags repeatedly reset for each pair of
bytes read. All changes that occur during a long read
sequence are detected and reported.
The INT output is not reasserted during a read
sequence to avoid recursive reentry into an interrupt
service routine. Instead, if a data change occurs that
would normally cause the INT output to be set, the INT
assertion is delayed until the STOP condition. INT is not
reasserted upon a STOP condition if the changed input
data is read before the STOP occurs. The INT logic
ensures that unnecessary interrupts are not asserted,
yet data changes are detected and reported no matter
when the change occurs.

MAX7327AATG+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Interface - I/O Expanders I2C PORT EXP&ER w/ 12 PUSH-PULL OUTPUTS
Lifecycle:
New from this manufacturer.
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