LTC1694-1CS5#TRMPBF

7
LTC1694-1
16941fa
APPLICATIONS INFORMATION
WUU
U
LTC1694-1
V
CC
GND
V
CC
5V
C1
0.1µF
SMBus1
SMBus2
1
2
5
4
LTC1694-1
V
CC
GND
SMBus1
SMBus2
5
4
1
2
SCL
SDA
DEVICE 1
CLK
IN
CLK
OUT
SMBus
DATA
IN
DATA
OUT
DEVICE N
1694-1 f03
CLK
IN
R
P2
CLK
OUT
DATA
IN
DATA
OUT
R
P1
Figure 3. Paralleling Two LTC1694-1 to Provide 4.4mA of Pull-Up Current
Using equations 4 and 5 to check exact value of t
r
:
t
r
= 0.535µs + 0.254µs = 0.79µs
Using equation 7 to check t
f
:
t
f
= 0.222µs
which is less than 0.3µs.
Using equation 1 to check V
OL
:
V
OL
= (3.3 • 700)/[700 + (27 • 10
3
)] = 83mV
which is less than 0.4V.
And using equation 2 to check the initial slew rate:
SR = 3.3/[(27 • 10
3
) • (200 • 10
–12
)] = 0.61V/µs
which is greater than 0.5V/µs.
Therefore, the value of R
P
chosen is 27k.
ACK Data Setup Time
Care must be taken in selecting the value of R
S
(in series
with the pull-down driver) to ensure that the data setup
time requirement for ACK (acknowledge) is fulfilled. An
acknowledge is accomplished by the SMBus host releas-
ing the SDA line (pulling high) at the end of the last bit sent
and the SMBus slave device pulling the SDA line low
before the rising edge of the ACK clock pulse.
The LTC1694-1 2.2mA pull-up current is activated when
the SMBus host releases the SDA line, allowing the
voltage to rise above the LTC1694-1’s comparator thresh-
old of 0.65V. If an SMBus slave device has a high value
of R
S
, a longer time is required for this SMBus slave
device to pull SDA low before the rising edge of the ACK
clock pulse.
To ensure sufficient data setup time for ACK, SMBus slave
devices with high values of R
S
, should pull the SDA low
earlier. Typically, a minimum setup time of 1.5µs is needed
for an SMBus device with an R
S
of 700 and a bus
capacitance of 200pF.
An alternative is that the SMBus slave device can hold SCL
line low until the SDA line reaches a stable state. Then, SCL
can be released to generate the ACK clock pulse.
Connecting Multiple LTC1694-1 in Parallel
The LTC1694-1 is designed to guarantee a maximum
SMBus rise time of 1µs with a bus capacitance of 200pF.
In some cases where the bus capacitance is higher than
200pF, multiple LTC1694-1s can be connected in parallel
to provide a higher pull-up current to meet the rise time
requirement. Figure 3 shows a typical application with two
LTC1694-1s connected in parallel to supply a pull-up
current of 4.4mA.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
8
LTC1694-1
16941fa
LT/TP 0304 REV A 1K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
APPLICATIONS INFORMATION
WUU
U
V
CC
= 5V 1µs/DIV
C
LD
= 200pF
f
SMBus
= 100kHz 1694 TA03
V
CC
= 3.3V 1µs/DIV
C
LD
= 200pF
f
SMBus
= 100kHz 1694 TA04
Comparison of SMBus Waveforms for the LTC1694-1 vs Resistor Pull-Up
R
PULL-UP
= 15.8k
LTC1694-1
1V/DIV
LTC1694-1
1V/DIV
R
PULL-UP
= 10.5k
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Swapping, Level Shifting
PACKAGE DESCRIPTION
U
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S5 TSOT-23 0302
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193

LTC1694-1CS5#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - Specialized SMBus/I2C Accelerator
Lifecycle:
New from this manufacturer.
Delivery:
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