ATTINY28L-4PI Datasheet ATTINY28L-4PU, ATTINY28V-1AU, ATTINY28V-1MU | P4-P6

ATtiny28L/V

1062FS–AVR–07/06

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

$3F SREG I T H S V N Z C page 6

$3E Reserved

... Reserved

$20 Reserved

$1F Reserved

$1E Reserved

$1D Reserved

$1C Reserved

$1B PORTA - - - - PORTA3 PORTA2 PORTA1 PORTA0 page 32

$1A PACR - - - - DDA3 PA2HC DDA1 DDA0 page 32

$19 PINA - - - -PINA3- PINA1 PINA0 page 32

$18 Reserved

$17 Reserved

$16 PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 32

$15 Reserved

$14 Reserved

$13 Reserved

$12 PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 33

$11 DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 33

$10 PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 33

$0F Reserved

$0E Reserved

$0D Reserved

$0C Reserved

$0B Reserved

$0A Reserved

$09 Reserved

$08 ACSR ACD -ACOACIACIE- ACIS1 ACIS0 page 44

$07 MCUCS PLUPB - SE SM WDRF - EXTRF PORF page 19

$06 ICR INT1 INT0 LLIE TOIE0 ISC11 ISC10 ISC01 ISC00 page 22

$05 IFR INTF1 INTF0 -TOV0- - - - page 23

$04 TCCR0 FOV0 - - OOM01 OOM00 CS02 CS01 CS00 page 35

$03 TCNT0 Timer/Counter0 (8-bit) page 36

$02 MODCR ONTIM4 ONTIM3 ONTIM2

ONTIM1

ONTIM0 MCONF2 MCONF1 MCONF0 page 43

$01 WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 page 37

$00 OSCCAL Oscillator Calibration Register page 9

ATtiny28L/V

1062FS–AVR–07/06

Instruction Set Summary

Mnemonic Operands Description Operation Flags # Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry Two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,H 1

SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd, K Clear Bit(s) in Register Rd ← Rd • (FFh - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd - 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← $FF None 1

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2

CP Rd, Rr Compare Rd - Rr Z,N,V,C,H 1

CPC Rd, Rr Compare with Carry Rd - Rr - C Z,N,V,C,H 1

CPI Rd, K Compare Register with Immediate Rd - K Z N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b) = 0) PC ← PC + 2 or 3 None 1/2

SBIS P, b Skip if Bit in I/O Register is Set if (P(b) = 1) PC ← PC + 2 or 3 None 1/2

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V = 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less than Zero, Signed if (N ⊕ V = 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half-carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T-flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T-flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2

ATtiny28L/V

1062FS–AVR–07/06

DATA TRANSFER INSTRUCTIONS

LD Rd, Z Load Register Indirect Rd ← (Z) None 2

ST Z, Rr Store Register Indirect (Z) ← Rr None 2

MOV Rd, Rr Move between Registers Rd ← Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

LPM Load Program Memory R0 ← (Z) None 3

BIT AND BIT-TEST INSTRUCTIONS

SBI P, b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left through Carry Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) Z,C,N,V 1

ROR Rd Rotate Right through Carry Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit Load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0C1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0N1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0Z1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0I1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0S1

SEV Set Two’s Complement Overflow V ← 1V1

CLV Clear Two’s Complement Overflow V ← 0V1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0T1

SEH Set Half-carry Flag in SREG H ← 1H1

CLH Clear Half-carry Flag in SREG H ← 0H1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

Instruction Set Summary (Continued)

Mnemonic Operands Description Operation Flags # Clocks

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

ATTINY28L-4PI

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