7
LTC1279
PI FU CTIO S
UU U
A
IN
(Pin 1): Analog Input. 0V to 5V (Unipolar), ±2.5V
(Bipolar).
V
REF
(Pin 2): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 11 to 4): Three-State Data Outputs.
D11 is the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
DV
DD
(Pin 17 ): Digital Power Supply, 5V. Tie to AV
DD
pin.
SHDN (Pin 18): Power Shutdown. The LTC1279 pow-
ers down when SHDN is low.
CONVST (Pin 19): Conversion Start Input. It is active
low. The falling edge of the CONVST signal initiates a
conversion. The LTC1279 responds to CONVST signal
only if the signal applied to CS is a logic low.
RD (Pin 20): READ Input. A logic low signal applied to
this pin enables the output data drivers when the signal
applied to the CS pin is a logic low.
CS (Pin 21): The CHIP SELECT input must be a logic low
for the ADC to recognize the signals applied to the
CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is a logic low during a conversion.
V
SS
(Pin 23): Negative Supply. –5V will select bipolar
operation. Bypass to AGND with 0.1µF ceramic. Tie to
analog ground to select unipolar operation.
AV
DD
(Pin 24): Positive Supply, 5V. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
FU CTIO AL BLOCK DIAGRA
UU W
12-BIT CAPACITIVE DAC
COMPAR-
ATOR
2.42V REF
V
REF
C
SAMPLE
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
•
•
D11
D0
BUSY
CONTROL LOGIC
CSCONVST RDSHDN
INTERNAL
CLOCK
ZEROING
SWITCH
DV
DD
V
SS
AV
DD
(0V FOR UNIPOLAR MODE
OR –5V FOR BIPOLAR MODE)
A
IN
AGND
DGND
12
12
1279 BD
8
LTC1279
TEST CIRCUITS
Load Circuits for Output Float DelayLoad Circuits for Access Timing
3k C
L
DBN
DGND
A) HIGH-Z TO V
OH
(t
8
)
AND V
OL
TO V
OH
(t
6
)
C
L
DBN
3k
5V
B) HIGH-Z TO V
OL
(t
8
)
AND V
OH
TO V
OL
(t
6
)
DGND
1279 TC01
3k
10pF
DBN
DGND
A) V
OH
TO HIGH-Z
10pF
DBN
3k
5V
B) V
OL
TO HIGH-Z
DGND
1279 TC02
CS to RD Setup Timing SHDN to CONVST Wake-Up Timing
CS to CONVST Setup Timing
TI I G DIAGRA S
WU W
APPLICATIONS INFORMATION
WUU
U
CONVERSION DETAILS
The LTC1279 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
input connects to the sample-and-hold
capacitor during the acquire phase, and the comparator
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 160ns will provide enough
V
DAC
1279 F01
+
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
12-BIT
LATCH
COMPAR-
ATOR
SAMPLE
SI
A
IN
Figure 1. A
IN
Input
t
3
SHDN
CONVST
1279 TD03
t
1
CS
RD
1279 TD01
t
2
CS
CONVST
1279 TD02
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches C
SAMPLE
to
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
9
LTC1279
APPLICATIONS INFORMATION
WUU
U
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the A
IN
input charge. The SAR contents (a 12-bit
data word) which represent the A
IN
are loaded into the
12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1279 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distor-
tion sine wave and analyzing the digital output using an
FFT algorithm, the ADC’s spectral content can be exam-
ined for frequencies outside the fundamental. Figures 2a
and 2b show typical LTC1279 FFT plots.
Figure 2b. LTC1279 Nonaveraged, 4096 Point FFT Plot
with 300kHz Input Frequency
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 600kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 300kHz as shown in Figure 2b.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 600kHz the LTC1279 maintains very good ENOBs up
to the Nyquist input frequency of 300kHz. Refer to Figure 3.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
Figure 3. Effective Bits and Signal/(Noise + Distortion) vs
Input Frequency
FREQUENCY (Hz)
10k
EFFECTIVE NUMBER OF BITS
SIGNAL/(NOISE + DISTORTION) (dB)
100k 1M 5M
1279 G03
12
11
10
9
8
7
6
5
4
3
2
1
0
74
68
62
56
50
f
SAMPLE
= 600kHz
NYQUIST
FREQUENCY
FREQUENCY (kHz)
0
AMPLITUDE (dB)
50
100 150 200
1279 F02a
250 300
0
10
20
30
40
50
60
70
80
90
100
110
120
f
SAMPLE
= 600kHz
f
IN
= 97.705kHz
FREQUENCY (kHz)
0
AMPLITUDE (dB)
50
100 150 200
1279 F02
250 300
0
10
20
30
40
50
60
70
80
90
100
110
120
f
SAMPLE
= 600kHz
f
IN
= 292.822kHz
Figure 2a. LTC1279 Nonaveraged, 4096 Point FFT Plot
with 100kHz Input Frequency

LTC1279IG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 600ksps Smpl A/D Conv w/ SD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union