M68EVB908QL4 Datasheet M68EVB908QL4 | P7-P9

M68EVB908QL4 12/04/03

POWER SUPPLY

Input power is applied by external connection to the PWR power jack or LIN-J1/2 port

connectors. The input source is selected by the PWR_SEL option jumper. The regulator is

protected from reverse voltage application by diode D3 or D4. Input voltage is regulated to

+5V supply by VR1 and enabled to the development board circuits by the +5V_EN option

jumper installed. The POWER indicator will light when +5V is available.

PWR_SEL Option

The PWR_SEL option provides EVB board input power source selection between the LIN port

connectors and primary input PWR jack. Default position is jumper installed on pins 1-2 for

PWR jack input. The user may elect to move this option jumper to position 2-3 when applying

the LIN ports on a LIN network that provides the +V source.

+5V_EN Option

The +5V_EN option provides board power enabled or disabled control. Default position is

jumper installed on both pins. The user may elect to remove this option jumper when a

Cyclone development cable is applied so that the cable can control the power up sequence.

POWER Indicator

The POWER indicator will be ON if +5V is available on the EVB board. The indicator may

have a visible indication if the power supply is below +5V and out of regulation also.

PWR - Power Jack

PWR provides the default power input to the board. The power jack accepts a standard 2.0 ~

2.1mm center barrel plug connector (positive voltage center) to provide the +V input supply of

+6 to +20 VDC (+9VDC typical).

U1 and U2 Sockets

U1 and U2 provide Zero Insertion Force (ZIF) type sockets for installing the QL4 device. Only

one QL4 maybe installed on the development board at a time. U1 provides a Dual In-Line

(DIP) type package mount and will also allow SOIC type packages to be applied with a SOIC /

DIP adapter (Logical Systems part # PA16SO1-03-3 or similar). U2 offers the TSSOP

package type mount. Use caution to verify the device PIN 1 location when installing in the

sockets.

+Volts, 2mm center

M68EVB908QL4 12/04/03

USER_COMPONENTS

Two push switches, potentiometer, and LED indicator are provided for user application.

JP1 USER OPTIONS

The JP1 option block provides a method to enable or connect user components to be applied

with the HC08 I/O ports. The development board user should be familiar with the input and

output application so that port conflicts do not occur. Following is the option connection

reference table:

POSITION USER COMPONENT HC08 PORT PORT

DIRECTION

ALTERNATE PORT

1 IRQ Push Switch PTA2/IRQ*/KBI2 Input MCU PORT pin 3,

MON_EN,

CYCLONE

2 RESET Push Switch PTA3/RST*/KBI3 Input MCU PORT pin 4

3 RV1 Potentiometer PTB3/AD5 Input MCU PORT pin 6

4 D1 Indicator (active low) PTB0/TCH0 Output MCU PORT pin 5

Note: RESET switch, IRQ switch, and LED indicator are active logic low.

RESET Switch

The RESET switch applies an active low signal to the HC08 PTA3/RST*/KBI3 pin if the JP1

option position 2 is installed. When applying the CYCLONE cable and port, this jumper should

be installed to enable the pull-up resistor on the RESET signal.

IRQ Switch

The IRQ switch applies an active low signal to the HC08 PTA2/IRQ*/KBI2 pin if the JP1 option

position 1 is installed.

RV1 User Potentiometer

The User Potentiometer provides an adjustable linear voltage from 0 to 5V. The voltage signal

is made available to HC08 port PTB3 / AD5 analog input by the JP1 position 3 option jumper

installed. The HC08 ADC module can measure the input voltage to allow user application

response to the input voltage level.

M68EVB908QL4 12/04/03

MON08 DEBUG PORT

The DEBUG port provides standard 9 pin connection with RS232 type serial interface to the

HC08 MON08 debug monitor. The MON_EN and CLK_EN options should be installed prior to

applying power to the EVB to apply the DEBUG port. HC08 ports PTA0, PTA2, and PTA5 are

applied to operate this port. Monitor communication is provided without additional features

such as BREAK or RESET. Hosting software is required to communicate with the monitor on

this port. Do not apply the DEBUG port and CYCLONE cable at the same time. Refer to the

M68EVB908QL4 schematic drawing for circuit and connector connections.

MON_EN Option

The MON_EN 1 and 2 option jumpers provide HC08 MON08 signals to the DEBUG Port.

Install the jumpers on both pins to enable the signals.

MON_EN 1 – Enables the 9V VTT supply to HC08 port PTA2/IRQ to enable monitor mode on

power up.

MON_EN 2 – Enables the MON08 communication from HC08 port PTA0 to the DEBUG port.

CLK_EN Option

The CLK_EN option jumper provides for a 9.8304Mhz clock to be applied to the HC08

PTA5/OSC1 pin. This clock source is required for MON08 debug monitor operation via the

DEBUG port. Install the jumper on both pins to enable the 9.8304 clock signal to the HC08.

X1 CLOCK OSCILLATOR

The X1 clock Oscillator is provided to allow default monitor mode (MON08) operation. When

the MON08 debug monitor is to be applied, the X1 clock should be optioned to provide the

clock source. The CLK_EN option jumper installed will provide the X1 clock source to the

HC08 device pin PTA5. User should also note that the MCU_PORT may provide a signal to

drive the clock signal on PTA5. In this case, the CLK_EN option should not be installed.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

M68EVB908QL4

Mfr. #:

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Development Boards & Kits - S08 / S12 MC68HC908QLX EVB

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