PCA9517AD,118 Datasheet PCA9517AD,118, PCA9517ATP,147, PCA9517ADP,118 | P4-P6

Product data sheet Rev. 4.1 — 24 May 2016 4 of 22

NXP Semiconductors

PCA9517A

Level translating I

C-bus repeater

5.2 Pin description

[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin

must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and

board level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board and for proper head conduction through the board, thermal vias need to be

incorporated in the printed-circuit board in the thermal pad region.

6. Functional description

Refer to Figure 1 “Functional diagram of PCA9517A”.

The PCA9517A enables I

C-bus or SMBus translation down to V

CC(A)

as low as 0.9 V

without degradation of system performance. The PCA9517A contains two bidirectional

open-drain buffers specifically designed to support up-translation/down-translation

between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I

C-bus or SMBus. All inputs

and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (V

CC(B)

and/or V

CC(A)

= 0 V). The PCA9517A includes a power-up circuit that keeps the output

drivers turned off until V

CC(B)

is above 2.5 V and the V

CC(A)

is above 0.8 V. V

CC(B)

and

CC(A)

can be applied in any sequence at power-up. After power-up and with the enable

(EN) HIGH, a LOW level on port A (below 0.3V

CC(A)

) turns the corresponding port B driver

(either SDA or SCL) on and drives port B down to about 0.5 V. When port A rises above

0.3V

CC(A)

, the port B pull-down driver is turned off and the external pull-up resistor pulls

the pin HIGH. When port B falls first and goes below 0.4 V the port A driver is turned on

and port A pulls down to 0 V. The port A pull-down is not enabled unless the port B

voltage goes below 0.4 V. If the port B low voltage goes below 0.4 V, the port B pull-down

driver is enabled and port B will only be able to rise to 0.5 V until port A rises above

0.3V

CC(A)

, then port B will continue to rise being pulled up by the external pull-up resistor.

The V

CC(A)

is only used to provide the 0.3V

CC(A)

reference to the port A input comparators

and for the power good detect circuit. The PCA9517A logic and all I/Os are powered by

the V

CC(B)

pin.

Table 3. Pin description

Symbol Pin Description

SO8,

TSSOP8

HWSON8

CC(A)

1 7 port A supply voltage (0.9 V to 5.5 V)

SCLA 2 8 serial clock port A bus

SDAA 3 1 serial data port A bus

GND 4 2

[1]

supply ground (0 V)

EN 5 3 active HIGH repeater enable input

SDAB 6 4 serial data port B bus

SCLB 7 5 serial clock port B bus

CC(B)

8 6 port B supply voltage (2.7 V to 5.5 V)

Product data sheet Rev. 4.1 — 24 May 2016 5 of 22

NXP Semiconductors

PCA9517A

Level translating I

C-bus repeater

6.1 Enable

The EN pin is active HIGH with an internal pull-up to V

CC(B)

and allows the user to select

when the repeater is active. This can be used to isolate a badly behaved slave on

power-up until after the system power-up reset. It should never change state during an

C-bus operation because disabling during a bus operation will hang the bus and

enabling part way through a bus cycle could confuse the I

C-bus parts being enabled.

The enable pin should only change state when the global bus and the repeater port are in

an idle state to prevent system failures.

6.2 I

C-bus systems

As with the standard I

C-bus system, pull-up resistors are required to provide the logic

HIGH levels on the buffered bus (standard open-collector configuration of the I

C-bus).

The size of these pull-up resistors depends on the system, but each side of the repeater

must have a pull-up resistor. This part designed to work with Standard mode and Fast

mode I

C-bus devices in addition to SMBus devices. Standard mode I

C-bus devices only

specify 3 mA output drive; this limits the termination current to 3 mA in a generic I

C-bus

system where Standard-mode devices and multiple masters are possible. Under certain

conditions higher termination currents can be used.

Please see Application Note AN255, I

C/SMBus Repeaters, Hubs and Expanders for

additional information on sizing resistors and precautions when using more than one

PCA9517A in a system or using the PCA9517A in conjunction with other bus buffers.

7. Application design-in information

A typical application is shown in Figure 5. In this example, the system master is running

on a 3.3 V I

C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.

Master devices can be placed on either bus.

The PCA9517A is 5 V tolerant, so it does not require any additional circuitry to translate

between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.

Fig 5. Typical application

002aad468

CC(A)

CC(B)

PCA9517A

SDAB SDAA

SCLB SCLA

10 kΩ

SDA

SCL

BUS

MASTER

400 kHz

SLAVE

400 kHz

SDA

SCL

bus B bus A

1.2 V

3.3 V

10 kΩ

Product data sheet Rev. 4.1 — 24 May 2016 6 of 22

NXP Semiconductors

PCA9517A

Level translating I

C-bus repeater

When port A of the PCA9517A is pulled LOW by a driver on the I

C-bus, a comparator

detects the falling edge when it goes below 0.3V

CC(A)

and causes the internal driver on

port B to turn on, causing port B to pull down to about 0.5 V. When port B of the

PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and causes

the internal driver on port A to turn on and pull the port A pin down to ground. In order to

illustrate what would be seen in a typical application, refer to Figure 9

and Figure 10. If the

bus master in Figure 5

were to write to the slave through the PCA9517A, waveforms

shown in Figure 9

would be observed on the A bus. This looks like a normal I

C-bus

transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn

off of the acknowledge signals are slightly delayed.

On the B bus side of the PCA9517A, the clock and data lines would have a positive offset

from ground equal to the V

of the PCA9517A. After the eighth clock pulse, the data line

will be pulled to the V

of the slave device which is very close to ground in this example.

At the end of the acknowledge, the level rises only to the LOW level set by the driver in the

PCA9517A for a short delay while the A bus side rises above 0.3V

CC(A)

then it continues

HIGH. It is important to note that any arbitration or clock stretching events require that the

LOW level on the B bus side at the input of the PCA9517A (V

) be at or below 0.4 V to be

recognized by the PCA9517A and then transmitted to the A bus side.

Multiple PCA9517A port A sides can be connected in a star configuration (Figure 6

allowing all nodes to communicate with each other.

Multiple PCA9517As can be connected in series (Figure 7

) as long as port A is connected

to port B. I

C-bus slave devices can be connected to any of the bus segments. The

number of devices that can be connected in series is limited by repeater

delay/time-of-flight considerations on the maximum bus speed requirements.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

PCA9517AD,118

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Manufacturer:

NXP Semiconductors

Description:

Interface - Signal Buffers, Repeaters LEVEL TRANSL I2C BUS

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PCA9517AD,118

PCA9517AD,118

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