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EP4CE22U14I7N

P1-P3P4-P6P7-P9P10-P12P13-P14
1–4 Chapter 1: Cyclone IV FPGA Device Family Overview
Device Resources
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Table 1–2 lists Cyclone IV GX device resources.
Table 1–2. Resources for the Cyclone IV GX Device Family
Resources
EP4CGX15
EP4CGX22
EP4CGX30
(1)
EP4CGX30
(2)
EP4CGX50
(3)
EP4CGX75
(3)
EP4CGX110
(3)
EP4CGX150
(3)
Logic elements (LEs) 14,400 21,280 29,440 29,440 49,888 73,920 109,424 149,760
Embedded memory (Kbits) 540 756 1,080 1,080 2,502 4,158 5,490 6,480
Embedded 18 × 18 multipliers 0 40 80 80 140 198 280 360
General purpose PLLs 1 2 2 4
(4)
4
(4)
4
(4)
4
(4)
4
(4)
Multipurpose PLLs 2
(5)
2
(5)
2
(5)
2
(5)
4
(5)
4
(5)
4
(5)
4
(5)
Global clock networks 20 20 20 30 30 30 30 30
High-speed transceivers
(6)
24448888
Transceiver maximum data rate
(Gbps)
2.5 2.5 2.5 3.125 3.125 3.125 3.125 3.125
PCIe (PIPE) hard IP blocks 11111111
User I/O banks 9
(7)
9
(7)
9
(7)
11
(8)
11
(8)
11
(8)
11
(8)
11
(8)
Maximum user I/O
(9)
72 150 150 290 310 310 475 475
Notes to Table 1–2:
(1) Applicable for the F169 and F324 packages.
(2) Applicable for the F484 package.
(3) Only two multipurpose PLLs for F484 package.
(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the Clock Networks and PLLs in
Cyclone IV Devices chapter.
(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer
to the Clock Networks and PLLs in Cyclone IV Devices chapter.
(6) If PCIe 1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.
(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.
(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.
(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
Chapter 1: Cyclone IV FPGA Device Family Overview 1–5
Package Matrix
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Package Matrix
Table 1–3 lists Cyclone IV E device package offerings.
Table 1–3. Package Offerings for the Cyclone IV E Device Family
(1),
(2)
Package E144 M164 M256 U256 F256 F324 U484 F484 F780
Size (mm) 22 × 22 8 × 8 9 x 9 14 × 14 17 × 17 19 x 19 19 × 19 23 × 23 29 × 29
Pitch (mm) 0.5 0.5 0.5 0.8 1.0 1.0 0.8 1.0 1.0
Device
User I/O
LVDS
(3)
User I/O
LVDS
(3)
User I/O
LVDS
(3)
User I/O
LVDS
(3)
User I/O
LVDS
(3)
User I/O
LVDS
(3)
User I/O
LVDS
(3)
User I/O
LVDS
(3)
User I/O
LVDS
(3)
EP4CE6 9121————1796617966————————
EP4CE109121————1796617966————————
EP4CE1581188921165531655316553————343137——
EP4CE227917————1535215352————————
EP4CE30 — — — — — — — — — — 193 68 — — 328 124 532 224
EP4CE40 — — — — — — — — — — 193 68 328 124 328 124 532 224
EP4CE55 — — — — — — — — — — — — 324 132 324 132 374 160
EP4CE75 — — — — — — — — — — — — 292 110 292 110 426 178
EP4CE115 — — — — — — — — — — ————280103528230
Notes to Table 1–3:
(1) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane of your PCB. Use this exposed pad for electrical
connectivity and not for thermal purposes.
(2) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more information, refer to the I/O
Management chapter in volume 2 of the Quartus II Handbook.
(3) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter.
1–6 Chapter 1: Cyclone IV FPGA Device Family Overview
Package Matrix
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Table 1–4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts.
Table 1–4. Package Offerings for the Cyclone IV GX Device Family
(1)
Package F169 F324 F484 F672 F896
Size (mm) 14 × 14 19 × 19 23 × 23 27 × 27 31 × 31
Pitch (mm) 1.0 1.0 1.0 1.0 1.0
Device
User I/O
LVDS
(2)
XCVRs
User I/O
LVDS
(2)
XCVRs
User I/O
LVDS
(2)
XCVRs
User I/O
LVDS
(2)
XCVRs
User I/O
LVDS
(2)
XCVRs
EP4CGX15 72 25 2 — — — — — — — — — — — —
EP4CGX22 72 25 2 150 64 4 — — — — — — — — —
EP4CGX30 72 25 2 150 64 4 290 130 4 — — — — — —
EP4CGX50 — — — — — — 290 130 4 310 140 8 — — —
EP4CGX75 — — — — — — 290 130 4 310 140 8 — — —
EP4CGX110 — — — — — — 270 120 4 393 181 8 475 220 8
EP4CGX150 — — — — — — 270 120 4 393 181 8 475 220 8
Note to Table 1–4:
(1) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more
information, refer to the I/O Management chapter in volume 2 of the Quartus II Handbook.
(2) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter.
P1-P3P4-P6P7-P9P10-P12P13-P14

EP4CE22U14I7N

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Buy EP4CE22U14I7N
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Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Cyclone IV E 1395 LABs 79 IOs
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New from this manufacturer.
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