1-to-2, LVCMOS/LVTTL-to-Differential
HSTL Translator
85222-02
DATASHEET
85222-02 REVISION B 6/15/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL
translator. The 85222-02 has one single ended clock input. The
single-ended clock input accepts LVCMOS or LVTTL input levels
and translates them to HSTL levels. The small outline 8-pin SOIC
package makes this device ideal for applications where space, high
performance and low power are important.
FEATURES
Two differential HSTL outputs
One LVCMOS/LVTTL clock input
CLK input can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 350MHz
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.25ns (maximum)
V
OH
: 1.4V (maximum)
Output crossover voltage: 0.68V - 0.9V
Full 3.3V operating supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in lead-free RoHS compliant package
BLOCK DIAGRAM PIN ASSIGNMENT
85222-02
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
VDD
CLK
nc
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
Pulldown
1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
85222-02 DATA SHEET
2 REVISION B 6/15/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1, 2 Q0, nQ0 Output Differential output pair. HSTL interface levels.
3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels.
5 GND Power Power supply ground.
6 nc Unused No connect.
7 CLK Input Pulldown LVCMOS / LVTTL clock input.
8V
DD
Power Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
NOTE: Unused output pairs must be terminated.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
REVISION B 6/15/15
85222-02 DATA SHEET
3 1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL
HSTL TRANSLATOR
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 70°C
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 70°C
TABLE 3C. HSTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
112.7°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 50 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current CLK V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current CLK V
DD
= 3.465, V
IN
= 0V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 1.0 1.4 V
V
OL
Output Low Voltage; NOTE 1 0 0.4 V
V
OX
Output Crossover Voltage 0.68 0.9 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 1.4 V
NOTE 1: All outputs must be terminated with 50Ω to ground.
TABLE 4. AC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay; NOTE 1 0.85 1.05 1.25 ns
tsk(o) Output Skew; NOTE 2, 3 25 ps
tsk(pp) Part-to-Part Skew; NOTE 4 250 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 500 ps
odc Output Duty Cycle
f 250MHz 45 55 %
f > 250MHz 40 60 %
All outputs must be terminated with 50W to ground.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

85222AM-02T

Mfr. #:
Manufacturer:
IDT
Description:
Translation - Voltage Levels
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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