MAX1715
Ultra-High Efficiency, Dual Step-Down
Controller for Notebook Computers
20 ______________________________________________________________________________________
power dissipation (PD) due to resistance occurs at
minimum battery voltage:
Generally, a small high-side MOSFET is desired in
order to reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation limits often limits how small the MOS-
FET can be. Again, the optimum occurs when the
switching (AC) losses equal the conduction (R
DS(ON)
)
losses. High-side switching losses don’t usually
become an issue until the input is greater than approxi-
mately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
2
F switching loss equation. If the high-side MOSFET
you’ve chosen for adequate R
DS(ON)
at low battery
voltages becomes extraordinarily hot when subjected
to V
IN(MAX)
, reconsider your choice of MOSFET.
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching loss calculation provides only a
very rough estimate and is no substitute for bread-
board evaluation, preferably including a verification
using a thermocouple mounted on Q1:
where C
RSS
is the reverse transfer capacitance of Q1
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
For the low-side MOSFET, Q2, the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
LOAD(MAX)
but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you must “overdesign” the
circuit to tolerate:
I
LOAD
= I
LIMIT(HIGH)
+ (LIR / 2)
✕
I
LOAD(MAX)
where I
LIMIT(HIGH)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. This means that
the MOSFETs must be very well heatsinked. If short-cir-
cuit protection without overload protection is enough, a
normal I
LOAD
value can be used for calculating com-
ponent stresses.
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general
rule, a diode having a DC current rating equal to 1/3 of
the load current is sufficient. This diode is optional and
can be removed if efficiency isn’t critical.
_________________Application Issues
Dropout Performance
The output voltage adjust range for continuous-con-
duction operation is restricted by the nonadjustable
500ns (max) minimum off-time one-shot. For best
dropout performance, use the slowest (200kHz) on-
time setting. When working with low input voltages, the
duty-factor limit must be calculated using worst-case
values for on- and off-times. Manufacturing tolerances
and internal propagation delays introduce an error to
the TON K-factor. This error is greater at higher fre-
quencies (Table 5). Also, keep in mind that transient
response performance of buck regulators operated
close to dropout is poor, and bulk output capacitance
must often be added (see the VSAG equation in the
Design Procedure).
Dropout design example: V
IN
= 3V min, V
OUT
= 2V, f
= 300kHz. The required duty is (V
OUT
+ V
SW
) / (V
IN
-
V
SW
) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The worst-
case on-time is (V
OUT
+ 0.075) / V
IN
✕
K = 2.075V / 3V
✕
3.35µs-V
✕
90% = 2.08µs. The IC duty-factor limitation
is:
which meets the required duty.
Remember to include inductor resistance and MOSFET
on-state voltage drops (V
SW
) when doing worst-case
dropout duty-factor calculations.
All-Ceramic-Capacitor Application
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR char-
acteristic can result in excessively high ESR zero fre-
quencies (affecting stability). In addition, their relatively
low capacitance value can cause output overshoot
