LTC4088-1/LTC4088-2
20
40881fc
applicaTions inForMaTion
In this circuit, capacitor C1 holds MP1 off when the cable
is first connected. Eventually the bottom plate of C1 dis-
charges to GND, applying increasing gate support to MP1.
The long time constant of R1 and C1 prevent the current
from building up in the cable too fast, thus dampening
out any resonant overshoot.
Voltage overshoot on V
BUS
may sometimes be observed
when connecting the LTC4088-1/LTC4088-2 to a lab power
supply. This overshoot is caused by long leads from the
power supply to V
BUS
. Twisting the wires together from
the supply to V
BUS
can greatly reduce the parasitic induc-
tance of these long leads, and keep the voltage at V
BUS
to
safe levels. USB cables are generally manufactured with
the power leads in close proximity, and thus fairly low
parasitic inductance.
Board Layout Considerations
The Exposed Pad on the backside of the LTC4088-1/
LTC4088-2 package must be securely soldered to the PC
board ground. This is the only ground pin in the pack-
age, and it serves as the return path for both the control
circuitry and the synchronous rectifier.
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitor, inductor, and
output capacitor be as close to the LTC4088-1/LTC4088-2
as possible and that there be an unbroken ground plane
under the LTC4088-1/LTC4088-2 and all of its external
high frequency components. High frequency currents,
such as the input current on the LTC4088-1/LTC4088-2,
tend to find their way on the ground plane along a mirror
path directly beneath the incident path on the top of the
board. If there are slits or cuts in the ground plane due to
other traces on that layer, the current will be forced to go
around the slits. If high frequency currents are not allowed
to flow back through their natural least-area path, exces-
sive voltage will build up and radiated emissions will occur
(see Figure 6). There should be a group of vias directly
under the grounded backside leading directly down to an
internal ground plane. To minimize parasitic inductance,
the ground plane should be as close as possible to the
top plane of the PC board (layer 2).
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA
of
leakage from this pin will introduce an additional offset
to the ideal diode of approximately 10mV. To minimize
leakage, the trace can be guarded on the PC board by
surrounding it with V
OUT
connected metal, which should
generally be less than one volt higher than GATE.
Figure 6. Ground Currents Follow Their Incident Path
at High Speed. Slices in the Ground Plane Cause High
Voltage and Increased Emissions
408812 F06
