NB3W800LMNGEVB Datasheet NB3W800LMNG, NB3W800LMNTWG, NB3W800LMNTXG | P1-P3

February, 2017 − Rev. 3

1 Publication Order Number:

NB3W800L/D

NB3W800L

3.3 V 100/133 MHz

Differential 1:8 HCSL-

Compatible Push-Pull Clock

ZDB/Fanout Buffer for PCIe

)

Description

The NB3W800L is a low−power 8−output differential buffer that

meets all the performance requirements of the DB800ZL

specification. The NB3W800L is capable of distributing the reference

clocks for Intel

QuickPath Interconnect (Intel QPI and UPI), PCIe

Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory

Interconnect (Intel SMI) applications. A fixed, internal feedback path

maintains low drift for critical QPI applications.

Features

• 8 Differential Clock Output Pairs @ 0.7 V

• Low−power NMOS Push−pull HCSL Compatible Outputs

• Cycle−to−cycle Jitter <50 ps

• Output−to−output Skew <50 ps

• Input−to−output Delay Variation <100 ps

• PCIe Phase Jitter: Gen3 <1.0 ps, Gen4 <0.5 ps RMS

• QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS

• Pseudo−External Fixed Feedback for Lowest Input−to−Output Delay

• Individual OE Control; Hardware Control of Each Output

• PLL Configurable for PLL Mode or Bypass Mode (Fanout

Operation)

• 100 MHz or 133 MHz PLL Mode Operation; Supports PCIe, QPI

and UPI Applications

• Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream

PLL’s

• SMBus Programmable Configurations

• Spread Spectrum Compatible; Tracks Input Clock Spreading for Low

EMI

• These are Pb−Free Devices

Device Package Shipping

†

ORDERING INFORMATION

NB3W800LMNG QFN48

(Pb−Free)

490 / Tray

CASE 485DP

MARKING

DIAGRAM

www.onsemi.com

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NB3W800L

AWLYYWWG

NB3W800L = Specific Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

NB3W800LMNTXG QFN48

(Pb−Free)

2500 / Tape &

Reel

481

NB3W800LMNTWG QFN48

(Pb−Free)

2500 / Tape &

Reel

NB3W800L

www.onsemi.com

Figure 1. Simplified Block Diagram

FB_OUT

DIF[7:0]

Control

Logic

CLK_IN

SSC Compatible

PLL

SDA

SCL

MUX

100M_133M#

PWRGD/PWRDN#

HBW_BYP_LBW#

OE[7:0]#

CLK_IN#

FB_OUT#

DIF[7:0]#

Table 1. OE AND POWER PIN TABLE

Inputs OE# Hardware Pins & Control Register Bits Outputs

PLL State

PWRGD/

PWRDN#

CLK_IN/

CLK_IN#

SMBUS

Enable Bit

OE# Pin

DIF/DIF# [7:0]

FB_OUT/

FB_OUT#

0 X X X Hi−Z Hi−Z OFF

1 Running

0 X Hi−Z Running ON

1 0 Running Running ON

1 1 Hi−Z Running ON

Table 2. FUNCTIONALITY AT POWER−UP (PLL MODE)

100M_133M# CLK_IN MHz DIF(7:0)

1 100.00 CLK_IN

0 133.33 CLK_IN

Table 3. POWER CONNECTIONS

Pin Number

Description

VDD GND

44 49 Analog PLL

3 2 Analog Input

10, 15, 19, 27, 34, 38, 42 49 DIF clocks

Table 4. SMBus ADDRESS

Address + Read/Write bit

D8 R

Table 5. PLL OPERATING MODE READBACK TABLE

HBW_BYP_LBW# Byte0, bit 7 Byte 0, bit 6

Low (Low BW) 0 0

Mid (Bypass) 0 1

High (High BW) 1 1

Table 6. TRI−LEVEL INPUT THRESHOLDS

Level Voltage

Low <0.8 V

Mid 1.2<Vin<1.8 V

High Vin > 2.2 V

Table 7. PLL OPERATING MODE

HBW_BYP_LBW# Mode

Low PLL Lo BW

Mid Bypass

High PLL Hi BW

NOTE: PLL is OFF in Bypass Mode

NB3W800L

www.onsemi.com

Figure 2. Pin Configuration

DIF6#

DIF6

VDD

DIF5#

DIF5

OE5#

OE4#

DIF4#

DIF4

VDD

DIF3#

DIF3

PWRGD/PWRDN#

VDDR

CLK_IN

CLK_IN#

SDA

GNDA

SCL

FB_OUT_NC#

FB_OUT_NC

VDD

OE0#

13 24

3748

HBW_BYP_LBW#

100M_133M#

VDDA

VDD

OE7#

DIF7#

DIF7

VDD

OE6#

DIF0

VDD

DIF1

DIF1#

OE1#

DIF0#

VDD

DIF2

DIF2#

OE2#

OE3#

Bottom EPAD

must be connected

to Ground

Table 8. PIN DESCRIPTIONS

Pin # Pin Name Type Description

1 PWRGD/PWRDN# IN 3.3 V Input notifies device to sample latched inputs and start up on first high assertion,

or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode.

2 GNDA GND Ground for Input Receiver and PLL Core

3 VDDR PWR 3.3 V power for differential input clock (receiver).

This VDD should be treated as an analog power rail and filtered appropriately.

4 CLK_IN IN 0.7 V Differential true input

5 CLK_IN# IN 0.7 V Differential complementary Input

6 SDA I/O Data pin of SMBus circuitry

7 SCL IN Clock pin of SMBus circuitry

8 FB_OUT_NC# OUT Complementary half of differential feedback output provides feedback signal to the PLL for

synchronization with input clock to eliminate phase error. This pin should NOT be connected on

the circuit board; the feedback is internal to the package.

9 FB_OUT_NC OUT True half of differential feedback output provides feedback signal to the PLL for synchronization

with the input clock to eliminate phase error. This pin should NOT be connected on the circuit

board; the feedback is internal to the package.

10 VDD PWR Power supply, nominal 3.3 V

11 OE0# IN

Active low input for enabling DIF pair 0. This pin has an internal pull−down.

1 = disable outputs, 0 = enable outputs

12 NC N/A No Connection.

13 DIF0 OUT 0.7 V differential true clock output

14 DIF0# OUT 0.7 V differential complementary clock output

15 VDD PWR Power supply, nominal 3.3 V

16 DIF1 OUT 0.7 V differential true clock output

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

NB3W800LMNGEVB

Mfr. #:

Buy NB3W800LMNGEVB

Manufacturer:

ON Semiconductor

Description:

Clock & Timer Development Tools 3.3 V 100/133 MHZ DIFFE

Lifecycle:

New from this manufacturer.

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NB3W800LMNGEVB

NB3W800LMNGEVB

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