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CS5101EDWR16G

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 6
1 Publication Order Number:
CS5101/D
CS5101
Secondary Side Post
Regulator for AC/DC and
DC/DC Multiple Output
Converters
The CS5101 is a bipolar monolithic secondary side post regulator
(SSPR) which provides tight regulation of multiple output voltages in
AC/DC or DC/DC converters. Leading edge pulse width modulation
is used with the CS5101.
The CS5101 is designed to operate over an 8.0 V to 45 V supply
voltage (V
CC
) range and up to a 75 V drive voltage (V
C
).
The CS5101 features include a totem pole output with 1.5 A peak
output current capability, externally programmable overcurrent
protection, an on chip 2.0% precision 5.0 V reference, internally
compensated error amplifier, externally synchronized switching
frequency, and a power switch drain voltage monitor. It is available in
a 14 lead plastic DIP or a 16 lead wide body SOIC package.
Features
• 1.5 A Peak Output (Grounded Totem Pole)
• 8.0 V to 75 V Gate Drive Voltage
• 8.0 V to 45 V Supply Voltage
• 300 ns Propagation Delay
• 1.0% Error Amplifier Reference Voltage
• Lossless Turn On and Turn Off
• Sleep Mode: < 100 mA
• Overcurrent Protection with Dedicated Differential Amp
• Synchronization to External Clock
• External Power Switch Drain Voltage Monitor
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
1
14
1
16
http://onsemi.com
PDIP−14
N SUFFIX
CASE 646
MARKING DIAGRAMS AND
PIN ASSIGNMENTS
SO−16WB
DW SUFFIX
CASE 751G
1
16
SO−16WB
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
V
D
SYNC
1
V
C
V
CC
V
G
V
REF
PGND
LGND
IS COMP
V
FB
IS−
COMP
IS+
RAMP
14
CS5101
AWLYYWWG
IS+RAMP
1
16
IS−COMP
IS COMPV
FB
PGNDAGND
PGNDDGND
V
G
V
REF
V
C
V
CC
V
D
SYNC
PDIP−14
CS5101EN14
AWLYYWWG
CS5101
http://onsemi.com
2
Figure 1. Application Diagram
V
SYNC
V
CC
V
REF
LGND
V
FB
COMP
RAMP
V
D
V
C
V
G
PGND
IS COMP
IS−
IS+
CS5101
SSPR
R12
R11
R9
R8
R14
R13
R6R5
GND
C6
V
OUT
L1
C
R5
Q1
+
V
SY
TR
C
R4
1 3
6
5
4
2
C
R1
R1 R2
+
C5
R7
C
R3
C4
R3
C
R2
C1
C2
R4
C
R
C3
+
R10
MAXIMUM RATINGS
Rating Value Unit
Power Supply Voltage, V
CC
−0.3 to 45 V
V
SYNC
and Output Supply Voltages, V
C
, V
G
, V
SYNC
, V
D
−0.3 to 75 V
V
IS+
, V
IS−
(V
CC
− 4.0 V, up to 24 V) −0.3 to 24 V
V
REF
, V
FB
, V
COMP
, V
RAMP
, V
ISCOMP
−0.3 to 10 V
Operating Junction Temperature, T
J
−40 to +150 °C
Operating Temperature Range −40 to +85 °C
Storage Temperature Range −65 to +150 °C
Output Energy (Capacitive Load Per Cycle) 5.0
mJ
ESD Human Body 2.0 kV
Lead Temperature Soldering Wave Solder (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
260 peak
230 peak
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 10 second maximum
2. 60 second maximum above 183°C
CS5101
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (−40°C ≤ T
A
≤ 85°C, −40°C ≤ T
J
≤ 150°C, 10 V < V
CC
< 45 V, 8.0 V < V
C
< 75 V; unless
otherwise specified.)
Characteristic Test Conditions Min Typ Max Unit
Error Amplifier
Input Voltage Initial Accuracy V
FB
= V
COMP
, V
CC
= 15 V, T = 25°C, Note 3 1.98 2.00 2.02 V
Input Voltage V
FB
= V
COMP
, includes line and temp 1.94 2.00 2.06 V
Input Bias Current V
FB
= 0 V, IV
FB
flows out of pin − − 500 nA
Open Loop Gain 1.5 V < V
COMP
< 3.0 V 60 70 − dB
Unity Gain Bandwidth 1.5 V < V
COMP
< 3.0 V, Note 3 0.7 1.0 − MHz
Output Sink Current V
COMP
= 2.0 V, V
FB
= 2.2 V 2.0 8.0 − mA
Output Source Current V
COMP
= 2.0 V, V
FB
= 1.8 V 2.0 6.0 − mA
V
COMP
High V
FB
= 1.8 V 3.3 3.5 3.7 V
V
COMP
Low V
FB
= 2.2 V 0.85 1.0 1.15 V
PSRR 10 V < V
CC
< 45 V, V
FB
= V
COMP
, Note 3 60 70 − dB
Voltage Reference
Output Voltage Initial Accuracy V
CC
= 15 V, T = 25°C, Note 3 4.9 5.0 5.1 V
Output Voltage 0 A < I
REF
< 8.0 mA 4.8 5.0 5.2 V
Line Regulation 10 V < V
CC
< 45 V, I
REF
= 0 A − 10 60 mV
Load Regulation 0 A < I
REF
< 8.0 mA − 20 60 mV
Current Limit V
REF
= 4.8 V 10 50 − mA
V
REF−
OK FAULT V V
SYNC
= 5.0 V, V
REF
= V
LOAD
4.10 4.40 4.60 V
V
REF−
OK V V
SYNC
= 5.0 V, V
REF
= V
LOAD
4.30 4.50 4.80 V
V
REF−
OK Hysteresis − 40 100 250 mV
Current Sense Amplifier
IS COMP High V IS+ = 5.0 V, IS− = IS COMP 4.7 5.0 5.3 V
IS COMP Low V IS+ = 0 V, IS− = IS COMP 0.5 1.0 1.3 V
Source Current IS+ = 5.0 V, IS− = 0 V 2.0 10 − mA
Sink Current IS− = 5.0 V, IS+ = 0 V 10 20 − mA
Open Loop Gain
1.5 V ≤ V
COMP
≤ 4.5 V, R
L
= 4.0 kW
60 80 − dB
CMRR Note 3 60 80 − dB
PSRR 10 V < V
CC
< 45 V, Note 3 60 80 − dB
Unity Gain Bandwidth
1.5 V ≤ V
COMP
≤ 4.5 V, R
L
= 4.0 kW, Note 3
0.5 0.8 − MHz
Input Offset Voltage V
IS
+ = 2.5 V, V
IS
− = V
ISCOMP
−8.0 0 8.0 mV
Input Bias Currents V
IS
+ = V
IS
− = 0 V, I
IS
flows out of pins − 20 250 nA
Input Offset Current (IS+, IS−) − −250 0 250 nA
Input Signal Voltage Range Note 3 −0.3 − V
CC
− 4.0 V
RAMP/SYNC Generator
RAMP Source Current Initial Accuracy V
SYNC
= 5.0 V, V
RAMP
= 2.5 V, T = 25°C, Note 3 0.18 0.20 0.22 mA
RAMP Source Current V
SYNC
= 5.0 V, V
RAMP
= 2.5 V 0.16 0.20 0.24 mA
RAMP Sink Current V
SYNC
= 0 V, V
RAMP
= 2.5 V 1.0 4.0 − mA
RAMP Peak Voltage V
SYNC
= 5.0 V 3.3 3.5 3.7 V
RAMP Valley Voltage V
SYNC
= 0 V 1.4 1.5 1.6 V
RAMP Dynamic Range V
RAMPDR
= V
RAMPPK
− V
RAMPVY
1.7 2.0 2.3 V
RAMP Sleep Threshold Voltage V
RAMP
@ V
REF
< 2.0 V 0.3 0.6 1.0 V
SYNC Threshold V
SYNC
@ V
RAMP
> 2.5 V 2.3 2.5 2.7 V
SYNC Input Bias Current V
SYNC
= 0 V, I
SYNC
flows out of pin − 1.0 20
mA
3. Guaranteed by design. Not 100% tested in production.
P1-P3P4-P6P7-P9

CS5101EDWR16G

Mfr. #:
Buy CS5101EDWR16G
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators Secondary Side 1.5A PWM AC/DC and DC/DC
Lifecycle:
New from this manufacturer.
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