PIC18F2XJXX/4XJXX FAMILY
DS30009687F-page 30 2008-2015 Microchip Technology Inc.
P1 TR MCLR Rise Time to Enter Program/Verify
mode
—1.0s
P2 T
PGC Serial Clock (PGC) Period 100 — ns
P2A T
PGCL Serial Clock (PGC) Low Time 50 — ns
P2B T
PGCH Serial Clock (PGC) High Time 50 — ns
P3 T
SET1 Input Data Setup Time to Serial Clock 20 — ns
P4 T
HLD1 Input Data Hold Time from PGC 20 — ns
P5 TDLY1 Delay Between 4-Bit Command and
Command Operand
50 — ns
P5A T
DLY1A Delay Between 4-Bit Command Operand and
Next 4-Bit Command
50 — ns
P6 T
DLY2 Delay Between Last PGC of Command
Byte to First PGC of Read of Data Word
20 — ns
P9 T
DLY5 Delay to allow Block Programming to occur 3.4 — ms PIC18F2XJ10/PIC18F4XJ10
1.2 — ms PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ5X/PIC18F4XJ5X
P10 T
DLY6 Delay to allow Row Erase to occur 49 — ms PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
54 — ms PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P11 T
DLY7 Delay to allow Bulk Erase to occur 475 — ms PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
524 — ms PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P12 T
HLD2 Input Data Hold Time from MCLR 400 — s
P13 T
SET2VDD Setup Time to MCLR 100 — ns
P14 T
VALID Data Out Valid from PGC 25 — ns
P16 T
DLY8 Delay between Last PGC and MCLR 20 — ns
P17 T
HLD3MCLR to VDD 3—s
P19 T
KEY1 Delay from First MCLR to First PGC for
Key Sequence on PGD
4—ms
P20 T
KEY2 Delay from Last PGC for Key Sequence on
PGD to Second MCLR
50 — ns
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Symbol Characteristic Min. Max. Units Conditions
Note 1: External power must be supplied to the V
DDCORE/VCAP pin if the on-chip voltage regulator is disabled. See
Section 2.1.1 “PIC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator” for
more information.
2: V
DD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of V
DD and VSS, respectively.