PIC18LF26J50T-I/ML Datasheet PIC18F25J50-I/SS, PIC18F26J50-I/ML, PIC18F26J50-I/SO | P16-P18

PIC18F2XJXX/4XJXX FAMILY

DS30009687F-page 16  2008-2015 Microchip Technology Inc.

4.0 READING THE DEVICE

4.1 Read Code Memory

Code memory is accessed one byte at a time via the

4-bit command, ‘1001’ (table read, post-increment).

The contents of memory pointed to by the Table Pointer

(TBLPTRU:TBLPTRH:TBLPTRL) are serially output on

PGD.

The 4-bit command is shifted in LSb first. The read is

executed during the next eight clocks, then shifted out

on PGD during the last eight clocks, LSb to MSb. A

delay of P6 must be introduced after the falling edge of

the 8th PGC of the operand to allow PGD to transition

from an input to an output. During this time, PGC must

be held low (see Figure 4-1). This operation also

increments the Table Pointer by one, pointing to the

next byte in code memory for the next read.

This technique will work to read any memory in the

000000h to 3FFFFFh address space, so it also applies

to reading the Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

FIGURE 4-1: TABLE READ, POST-INCREMENT INSTRUCTION TIMING (1001)

4-Bit

Command

Data Payload Core Instruction

Step 1: Set Table Pointer.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW Addr[21:16]

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 2: Read memory and then shift out on PGD, LSb to MSb.

1001 00 00 TBLRD *+

1234

PGC

PGD

PGD = Input

Shift Data Out

PGD = Output

5678

1234

P5A

10 11 13 15 161412

Fetch Next 4-Bit Command

1001

PGD = Input

LSb

MSb

1234

nnnn

P14

 2008-2015 Microchip Technology Inc. DS30009687F-page 17

PIC18F2XJXX/4XJXX FAMILY

4.2 Verify Code Memory and

Configuration Word

The verify step involves reading back the code memory

space and comparing it against the copy held in the

programmer’s buffer. Because the Flash Configuration

Words are stored at the end of program memory, it is

verified with the rest of the code at this time.

The verify process is shown in the flowchart in

Figure 4-2. Memory reads occur a single byte at a time,

so two bytes must be read to compare against the word

in the programmer’s buffer. Refer to Section 4.1

“Read Code Memory” for implementation details of

reading code memory.

FIGURE 4-2: VERIFY CODE

MEMORY FLOW

4.3 Blank Check

The term Blank Check means to verify that the device

has no programmed memory cells. All memories, code

memory and Configuration bits, must be verified. The

Device ID registers (3FFFFEh:3FFFFFh) should be

ignored.

A “blank” or “erased” memory cell will read as a ‘1’, so

Blank Checking a device merely means to verify that all

bytes read as FFh. The overall process flow is shown

in Figure 4-3.

Blank Checking is merely code verification with FFh

expect data. For implementation details, refer to

Section 4.2 “Verify Code Memory and Configuration

Word”.

FIGURE 4-3: BLANK CHECK FLOW

Note 1: Because the Flash Configuration Word

contains the device code protection bit,

code memory should be verified

immediately after writing if code protection

is enabled. This is because the device will

not be readable or verifiable if a device

Reset occurs after the Flash Configuration

Words (and the CP0 bit) have been

cleared.

Read Low Byte

Read High Byte

Does

Word = Expect

Data?

Failure,

Report

Error

All

Code Memory

Verified?

Yes

Set TBLPTR = 0

Start

Yes

Done

with Post-Increment

Yes

Start

Blank Check Device

Device

Blank?

Continue

Abort

PIC18F2XJXX/4XJXX FAMILY

DS30009687F-page 18  2008-2015 Microchip Technology Inc.

5.0 CONFIGURATION WORD

The Configuration Words of the PIC18F2XJXX/4XJXX

Family devices are implemented as volatile memory

registers. All of the Configuration registers (CONFIG1L,

CONFIG1H, CONFIG2L, CONFIG2H, CONFIG3L,

CONFIG3H, CONFIG4L, and CONFIG4H) are

automatically loaded following each device Reset.

The data for these registers is taken from the four Flash

Configuration Words located at the end of program

memory. Configuration data is stored in order, starting

with CONFIG1L in the lowest Flash address and

ending with CONFIG4H in the highest. The mapping to

specific Configuration Words is shown in Table 5-1.

Users should always reserve these locations for

Configuration Word data and write their application

code accordingly.

The upper four bits of each Flash Configuration Word

should always be stored in program memory as ‘1111’.

This is done so these program memory addresses will

always be ‘1111 xxxx xxxx xxxx’ and interpreted

as a NOP instruction if they were ever to be executed.

Because the corresponding bits in the Configuration

registers are unimplemented, they will not change the

device’s configuration.

The Configuration and Device ID registers are

summarized in Table 5-2. A listing of the individual

Configuration bits and their options is provided in

Table 5-3.

TABLE 5-1: MAPPING OF THE FLASH

CONFIGURATION WORDS TO

THE CONFIGURATION

REGISTERS

TABLE 5-2: PIC18F45J10 FAMILY DEVICES: CONFIGURATION BITS AND DEVICE IDs

Configuration

Flash

Configuration

Byte

(1)

Configuration

Address

CONFIG1L XFF8h 300000h

CONFIG1H XFF9h 300001h

CONFIG2L XFFAh 300002h

CONFIG2H XFFBh 300003h

CONFIG3L XFFCh 300004h

CONFIG3H XFFDh 300005h

CONFIG4L

(2)

XFFEh 300006h

CONFIG4H

(2)

XFFFh 300007h

Note 1: See Table 2-2 for the complete addresses

within code space for specific devices and

memory sizes.

2: Unimplemented in PIC18F45J10 family

devices.

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default/

Unprogrammed

Value

300000h CONFIG1L DEBUG

XINST STVREN — — — —WDTEN111- ---1

300001h CONFIG1H

—

(1)

—

(1)

—

(1)

—

(1)

—

(2)

CP0 — — ---- 01--

300002h CONFIG2L IESO FCMEN

— — —FOSC2FOSC1FOSC011-- -111

300003h CONFIG2H

—

(1)

—

(1)

—

(1)

—

(1)

WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111

300005h CONFIG3H

—

(1)

—

(1)

—

(1)

—

(1)

— — —CCP2MX---- ---1

3FFFFEh DEVID1

(3)

DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 See Table

3FFFFFh DEVID2

(3)

DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 See Table

Legend: - = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if

it is accidentally executed.

2: This bit should always be maintained at ‘0’.

3: DEVID registers are read-only and cannot be programmed by the user.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

PIC18LF26J50T-I/ML

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