LTC3860EUH#PBF Datasheet LTC3860EUH#PBF, LTC3860EUH#TRPBF, LTC3860IUH#TRPBF | P10-P12

LTC3860

3860fc

OPERATION

(Refer to Functional Diagram)

Main Control Architecture

The LTC3860 is a dual-channel/dual-phase, constant

frequency, voltage mode controller for DC/DC step-down

applications. It is designed to be used in a synchronous

switching architecture with external integrated-driver

MOSFETs or external drivers and N-channel MOSFETs

using single wire three-state PWM interfaces. The

controller allows the use of sense resistors or lossless

inductor DCR current sensing to maintain current balance

between phases and to provide overcurrent protection.

The operating frequency is selectable from 250kHz to

1.25MHz. To multiply the effective switching frequency,

multiphase operation can be extended to 3, 4, 6, or 12

phases by paralleling up to 6 controllers. In single or 3-

phase operation, the 2nd or 4th channel can be used as

an independent output.

The output of the differential ampliﬁ er is connected to

the error ampliﬁ er inverting input (FB) through a resistor

divider. The remote sense differential ampliﬁ er output

SNSOUT

) provides a signal equal to the differential voltage

SNSP

– V

SNSN

) sensed across the output capacitor, but

re-referenced to the local ground (SGND). This permits

accurate voltage sensing at the load, without regard to

the potential difference between its ground and local

ground.

In the main voltage mode control loop, the error ampli-

ﬁ er output (COMP) directly controls the converter duty

cycle in order to drive the FB pin to 0.6V in steady state.

Dynamic changes in output load current can perturb the

output voltage. When the output is below regulation,

COMP rises, increasing the duty cycle. If the output rises

above regulation, COMP will decrease, decreasing the

duty cycle. As the output approaches regulation, COMP

will settle to the steady-state value representing the step-

down conversion ratio.

In normal operation, the PWM latch is set high at the begin-

ning of the clock cycle (assuming COMP > 0.5V). When

the (line feedforward compensated) PWM ramp exceeds

the COMP voltage, the comparator trips and resets the

PWM latch. If COMP is less than 0.5V at the beginning

of the clock cycle, as in the case of an overvoltage at the

outputs, the PWM pin remains low throughout the entire

cycle. When the PWM pin goes high it has a minimum

on-time of approximately 20ns and a minimum off-time

of approximately 1/12th the switching period.

Current Sharing

In multiphase operation, the LTC3860 also incorporates an

auxiliary current sharing loop. Inductor current is sampled

each cycle. The master’s current sense ampliﬁ er output

is averaged at the I

AVG

pin. A small capacitor connected

from I

AVG

to GND (typically 100pF) stores a voltage cor-

responding to the instantaneous average current of the

master. Each phase integrates the difference between its

current and the master’s. Within each phase the integrator

output is proportionally summed with the system error

ampliﬁ er voltage (COMP), adjusting that phase’s duty

cycle to equalize the currents. When multiple ICs are

daisychained the I

AVG

pins must be connected together.

When the phases are operated independently, the I

AVG

pin should be tied to ground. Figure 1 shows a transient

load step with 50% inductor mismatch in a 2-phase system.

Figure 1

OUT(AC)

100mV/DIV

50μs/DIV

3860 F01

= 12V

OUT

= 1.2V

LOAD

= 0A TO 25A

= 320nH

10A/DIV

LOAD

20A/DIV

= 220nH

10A/DIV

Overcurrent Protection

The current sense ampliﬁ er outputs also connect to

overcurrent (OC) comparators that provide fault protec-

tion in the case of an output short. When an OC fault is

detected, the controller three-states the PWM output,

resets the soft-start capacitor, and waits for 32768 clock

cycles before attempting to start up again. The LTC3860

also provides negative OC (NOC) protection by preventing

turn-on of the bottom MOSFET during a negative OC fault

condition. The negative OC threshold is equal to –3/4 the

positive OC threshold. See Applications Information for

guidelines on setting these thresholds.

LTC3860

3860fc

Excellent Transient Response

The LTC3860 error ampliﬁ ers are true operational ampli-

ﬁ ers, meaning that they have high bandwidth, high DC gain,

low offset and low output impedance. Their bandwidth,

when combined with high switching frequencies and low-

value inductors, allows the compensation network to be

optimized for very high control loop crossover frequencies

and excellent transient response. The 600mV internal ref-

erence allows regulated output voltages as low as 600mV

without external level-shifting ampliﬁ ers.

Line Feedforward Compensation

The LTC3860 achieves outstanding line transient response

using a feedforward correction scheme which instanta-

neously adjusts the duty cycle to compensate for changes

in input voltage, signiﬁ cantly reducing output overshoot

and undershoot. It has the added advantage of making

the DC loop gain independent of input voltage. Figure 2

shows how large transient steps at the input have little

effect on the output voltage.

Shutdown Control Using the RUN Pins

The two channels of the LTC3860 can be independently

enabled using the RUN1 and RUN2 pins. When both pins

are driven low all internal circuitry, including the internal

reference and oscillator, are completely shut down. A 1.5μA

pull-up current is provided for each RUN pin internally.

The RUN pins remain low impedance up to V

. From V

to 6V, they may sink some current.

Undervoltage Lockout

To prevent operation of the power supply below safe input

voltage levels, both channels are disabled when V

is below

the undervoltage lockout (UVLO) threshold (2.9V falling,

3V rising). If a RUN pin is driven high, the LTC3860 will

start up the reference to detect when V

rises above the

UVLO threshold, and enable the appropriate channel.

Overvoltage Protection

If the output voltage rises to more than 10% above the

set regulation value, which is reﬂ ected as a V

voltage of

0.66V or above, the LTC3860 will force the PWM output

low to turn on the bottom MOSFET and discharge the

output. Normal operation resumes once the output is

back within the regulation window. However, if the reverse

current ﬂ owing from V

OUT

back through the bottom power

MOSFET to PGND is greater than 3/4 the positive OC

threshold, the NOC comparator trips and shuts off the

bottom power MOSFET to protect it from being destroyed.

This scenario can happen when the LTC3860 tries to start

into a precharged load, higher than the OV threshold. As

a result, the bottom switch turns on until the amount of

reverse current trips the NOC comparator threshold.

Internal Soft-Start

By default, the start-up of each channel’s output voltage

is normally controlled by an internal soft-start ramp. The

internal soft-start ramp represents a noninverting input

to the error ampliﬁ er. The FB pin is regulated to the lower

of the error ampliﬁ er’s three noninverting inputs (the

internal soft-start ramp for that channel, the TRACK/SS

pin or the internal 600mV reference). As the ramp volt-

age rises from 0V to 0.6V over approximately 2ms, the

output voltage rises smoothly from its prebiased value to

its ﬁ nal set value.

OPERATION

(Refer to Functional Diagram)

Figure 2

20μs/DIV

OUT

= 1.2V

STEP = 7V TO 14V

3860 F02

OUT

50mV/DIV

2A/DIV

5V/DIV

COMP1

100mV/DIV

Remote Sense Differential Ampliﬁ er

The LTC3860 includes a low offset, unity gain, high

bandwidth differential ampliﬁ er for remote output sens-

ing. Output voltage accuracy is signiﬁ cantly improved

by removing board interconnection losses from the total

error budget.

The LTC3860 differential ampliﬁ er has a typical output

slew rate of 45V/μs, bandwidth of 20MHz, input referred

offset < 2mV and a typical maximum output voltage of V

– 1V. The ampliﬁ er is conﬁ gured for unity gain, meaning

that the differential voltage between V

SNSP

and V

SNSN

translated to V

SNSOUT

, relative to SGND.

LTC3860

3860fc

Certain applications can result in the start-up of the

converter into a non-zero load voltage, where residual

charge is stored on the output capacitor at the onset of

converter switching. In order to prevent the output from

discharging under these conditions, the bottom MOSFET

is disabled until soft-start is complete. However, the bot-

tom MOSFET will be turned on for 20ns every 8 cycles

to allow the driver IC to recharge its topside gate drive

capacitor.

Soft-Start and Tracking Using TRACK/SS Pin

The user can connect an external capacitor greater than

10nF to the TRACK/SS pin for the relevant channel to

increase the soft-start ramp time beyond the internally set

default. The TRACK/SS pin represents a noninverting input

to the error ampliﬁ er and behaves identically to the internal

ramp described in the previous section. An internal 2.5μA

current source charges the capacitor, creating a voltage

ramp on the TRACK/SS pin. As the TRACK/SS pin voltage

rises from 0V to 0.6V, the output voltage rises smoothly

from 0V to its ﬁ nal value in:

• 0.6V

2.5µA

seconds

Alternatively, the TRACK/SS pin can be used to force the

start-up of V

OUT

to track the voltage of another supply.

Typically this requires connecting the TRACK/SS pin to

an external divider from the other supply to ground (see

Applications Information). It is only possible to track

another supply that is slower than the internal soft-start

ramp. The TRACK/SS pin also has an internal open-drain

NMOS pull-down transistor that turns on to reset the

TRACK/SS voltage when the channel is shut down (RUN

= 0V or V

< UVLO threshold) or during an OC fault

condition.

In multiphase operation, one master error ampliﬁ er is

used to control all of the PWM comparators. The FB pins

for the unused error ampliﬁ ers are connected to V

order to three-state these ampliﬁ er outputs, and the COMP

pins are connected together. The TRACK/SS pins should

also be connected together so that the slave phases can

detect when soft-start is complete and enable the bottom

MOSFET.

Frequency Selection and the Phase-Locked Loop (PLL)

The selection of the switching frequency is a trade-off

between efﬁ ciency, transient response and component

size. High frequency operation reduces the size of the

inductor and output capacitor as well as increasing the

maximum practical control loop bandwidth. However,

efﬁ ciency is generally lower due to increased transition

and switching losses.

The LTC3860’s switching frequency can be set in three

ways: using an external resistor to linearly program the

frequency, synchronizing to an external clock, or simply

selecting one of two ﬁ xed frequencies (400kHz and

600kHz). Table 1 highlights these modes.

Table 1. Frequency Selection

CLKIN PIN FREQ PIN FREQUENCY

Clocked R

FREQ

to GND 250kHz to 1.25MHz

High R

FREQ

to GND 250kHz to 1.25MHz

Low Low 400kHz

Low High 600kHz

No external PLL ﬁ lter is required to synchronize the

LTC3860 to an external clock. Applying an external clock

signal to the CLKIN pin will automatically enable the PLL

with internal ﬁ lter.

Constant frequency operation brings with it a number of

beneﬁ ts: inductor and capacitor values can be chosen

for a precise operating frequency and the feedback loop

can be similarly tightly speciﬁ ed. Noise generated by the

circuit will always be at known frequencies.

Using the CLKOUT and PHSMD Pins in

Multiphase Applications

The LTC3860 features CLKOUT and PHSMD pins that al-

low multiple LTC3860 ICs to be daisychained together in

multiphase applications. The clock output signal on the

CLKOUT pin can be used to synchronize additional ICs in

a 3-, 4-, 6- or 12-phase power supply solution feeding a

single high current output, or even several outputs from

the same input supply.

The PHSMD pin is used to adjust the phase relationship

between channel 1 and channel 2, as well as the phase

OPERATION

(Refer to Functional Diagram)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

LTC3860EUH#PBF

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Switching Voltage Regulators Dual-Phase/Dual-Channel Step-Down Voltage Mode Controller with Current Sharing

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