NB4L339
http://onsemi.com
6
Table 8. AC CHARACTERISTICS V
CC
= 2.375 V to 3.6 V, V
EE
= 0 V (Note 9)
Symbol Characteristic
−40_C 25_C 85_C
Unit
Min Typ Max Min Typ Max Min Typ Max
fin
max
Maximum Input CLOCK Frequency 700 700 700 MHz
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
)
(See Figure 4) f
in
≤ 622 MHz 530 730 530 730 530 730
mV
t
PLH
,
t
PHL
Propagation Delay to CLKx/CLKx to Qx/Qx
Output Differential ÷ 1MR to Qx
CLKSEL to Qx
0.8
1.2
0.8
1.0
−
1.0
1.3
5.0
1.3
0.8
1.2
0.8
1.0
−
1.0
1.3
5.0
1.3
0.8
1.2
0.8
1.0
−
1.0
1.3
5.0
1.3
ns
trr Reset Recovery 4.0 4.0 4.0 ns
DCO Output CLOCK Duty Cycle All Divides 40 60 40 60 40 60 %
t
SKEW
Within Device Skew (Note 11)
Device to Device Skew (Note 12)
30
90
60
190
30
90
60
190
30
90
60
190
ps
t
s
Setup Time @ 50 MHz EN to CLKx
DIVSEL to CLKx
900
−100
900
−100
900
−100
ps
t
h
Hold Time @ 50 MHz CLKx to EN
CLKx to DIVSEL
800
0
800
0
800
0
ps
t
PW
Minimum Pulse Width MR 5.0 5.0 5.0 ns
N
Phase Noise f
in
= 622.08 MHz
Outputs (A) Div by 1
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
−136
−136
−141
−141
−141
−141
dBc
t
JIT1
Integrated Phase Jitter (Figure 4)
f
in
= 622.08 MHz, 12 kHz − 20 MHz Offset
All Divides 0.15 0.25 0.15 0.25 0.15 0.25
ps
RMS
t
JIT2
Random Clock Period Jitter (Note 13)
f
in
= 622.08 MHz All Divides 0.5 1.5 0.5 1.5 0.5 1.5
ps
RMS
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14)
150 150 150 mV
t
r
, t
f
Output Rise/Fall Times @ 622.08 MHz
input frequency (20% − 80%)
150 250 150 250 150 250 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing V
INPP
(Min) from a 50% duty cycle clock source. All loading with an external R
L
= 50 to V
CC
− 2 V Input edge rates
100 ps (20% − 80%).
10.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 50 MHz.
11. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from the cross−point of the inputs to the cross−point of the outputs.
12.Device to device skew is measured between outputs under identical transition @ 50 MHz.
13.Additive RMS jitter with 50% duty cycle clock signal; all inputs and outputs active.
14.V
INPP
(Max) cannot exceed V
CC
− V
EE
. Input voltage swing is a single−ended measurement operating in differential mode.
