Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. B
11/23/2010
IS62C51216AL
IS65C51216AL
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
512K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns, 55ns
• CMOS low power operation
– 36 mW (typical) operating
– 12 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
– 4.5V--5.5V V
dd
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Automotive temperature (-40
o
C to +125
o
C)
• Lead-free available
DESCRIPTION
The ISSI IS62C51216AL and IS65C51216AL are high-
speed, 8M bit static RAMs organized as 512K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable (WE)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB) and Lower Byte (LB) access.
The IS62C51216AL and IS65C51216AL are packaged in
the JEDEC standard 48-pin mini BGA (9mm x 11mm) and
44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
DECEMBER 2010
A0-A18
CS1
OE
WE
512K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
