11
LTC1588/LTC1589/LTC1592
1588992fa
APPLICATIO S I FOR ATIO
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Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1592, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 2 and 3 contain equations for evaluating the effects
of op amp parameters on the LTC1592’s accuracy when
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the INL, DNL,
unipolar offset, unipolar gain error, bipolar zero and bipo-
lar gain error. Tables 2 and 3 can also be used to determine
the effects of op amp parameters on the LTC1589 and the
LTC1588. However, the results obtained from Tables 2
and 3 are in 16-bit LSBs. Divide these results by 4
(LTC1589) and 16 (LTC1588) to obtain the correct LSB
sizing.
Table 4 contains a partial list of LTC precision op amps
recommended for use with the LTC1592. The easy-to-use
design equations simplify the selection of op amps to meet
the system’s specified error budget. Select the amplifier
from Table 4 and insert the specified op amp parameters
in Table 3. Add up all the errors for each category to
determine the effect the op amp has on the accuracy of the
LTC1592. Arithmetic summation gives an (unlikely) worst-
case effect. A root-sum-square (RMS) summation pro-
duces a more realistic estimate.
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For the
LTC1592, a 250µV op amp offset will cause about 0.65LSB
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range (20V range in bipolar). For the LTC1592
programmed in a unipolar mode, the same 250µV op amp
offset will cause a 3.3LSB zero-scale error and a 3.3LSB
gain error with a 10V full-scale range.
CS/LD goes high, the mode changes and the DAC output
goes to a value corresponding to the data code.
Examples using the LTC1592:
1. Using a 24-bit loading sequence, load the unipolar
range of 0V to 10V with the DAC output at zero volt:
a) CS/LD
b) Clock SDI = 1001 XXXX 0000 0000 0000 0000
c) CS/LD ; then V
OUT
= 0V
2. Using a 24-bit loading sequence, load the bipolar range
of ±5V and the DAC output at zero volt:
a) CS/LD
b) Clock SDI = 1010 XXXX 1000 0000 0000 0000
c) CS/LD ; then V
OUT
= 0V on the ±5V range
3. Using a 32-bit load sequence, load the bipolar range of
±10V with the DAC output voltage at 5V initially. Then
change the DAC output to –5V:
a) CS/LD
b) Clock SDI = XXXX XXXX 1011 XXXX 1100 0000 0000
0000
c) CS/LD ; then V
OUT
= 5V on the ±10V range
Next, the bipolar range of ±10V is retained and the DAC
output voltage is changed to V
OUT
= –5V:
a) CS/LD
b) Clock SDI = XXXX XXXX 0010 XXXX 0100 0000 0000
0000
c) CS/LD ; then V
OUT
= –5V on the ±10V range
OPERATIO
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