RT9728A
10
DS9728A-06 November 2013www.richtek.com
©
Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Chip Enable Input
The RT9728AH/L will be disabled when the EN/EN pin is
in a logic-low/high condition. During this condition, the
internal circuitry and MOSFET are turned off, reducing
the supply current to 1μA typical. The maximum
guaranteed voltage for a logic-low at the EN/EN pin is
0.66V. A minimum guaranteed voltage of 1.1V at the EN/
EN pin will turn off the RT9728A. Floating the input may
cause unpredictable operation. EN/EN should not be
allowed to go negative with respect to GND.
Under Voltage Lockout
Under voltage lockout (UVLO) prevents the MOSFET
switch from turning on until input voltage exceeds
approximately 2.3V. If input voltage drops below
approximately 2.1V, UVLO turns off the MOSFET switch
and FAULT will be asserted accordingly. The under voltage
lockout detection functions only when the switch is
enabled.
Fault Flag
The RT9728A provides a FAULT signal pin which is an N-
channel open drain MOSFET output. This open drain output
goes low when current exceeds current limit threshold,
V
OUT
− V
IN
exceeds reverse voltage trip level, or the die
temperature exceeds 160°C approximately. The FAULT
output is capable of sinking a 1mA load to typically 180mV
above ground. The FAULT pin requires a pull-up resistor;
this resistor should be large in value to reduce energy
drain. A 100kΩ pull-up resistor works well for most
applications. In case of an over current condition, FAULT
will be asserted only after the flag response delay time,
tD, has elapsed. This ensures that FAULT is asserted upon
valid over current conditions and that erroneous error
reporting is eliminated. For example, false over current
conditions may occur during hot-plug events when
extremely large capacitive loads are connected, which
induces a high transient inrush current that exceeds the
current limit threshold. The FAULT response delay time,
t
D
, is typically 7.5ms.
Supply Filter/Bypass Capacitor
A 10μF low ESR ceramic capacitor connected from V
IN
to
GND and located close to the device is strongly
recommended to prevent input voltage drooping during hot-
plug events. However, higher capacitor values may be used
to further reduce the voltage droop on the input. Without
this bypass capacitor, an output short may cause sufficient
ringing on the input (from source lead inductance) to
destroy the internal control circuitry. Note that the input
transient voltage must never exceed 6V as stated in the
Absolute Maximum Ratings.
Output Filter Capacitor
A low ESR 150μF aluminum electrolytic capacitor
connected between V
OUT
and GND is strongly
recommended to meet the USB standard maximum droop
requirement for the hub, VBUS. Standard bypass methods
should be used to minimize inductance and resistance
between the bypass capacitor and the downstream
connector to reduce EMI and decouple voltage droop
caused by hot-insertion transients in downstream cables.
Ferrite beads in series with VBUS, the ground line and
the 0.1μF bypass capacitors at the power connector pins
are recommended for EMI and ESD protection. The bypass
capacitor itself should have a low dissipation factor to allow
decoupling at higher frequencies.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOT-23-6 packages, the thermal resistance, θ
JA
, is 250°C/
W on a standard JEDEC 51-3 single-layer thermal test
board. For WDFN-6L 2x2 packages, the thermal
resistance, θ
JA
, is 165°C/W on a standard JEDEC 51-3
