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DAC1401D125HL-C1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
DAC1401D125 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 16 of 25
Integrated Device Technology
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
10.2.2 Interleaved mode
The data and clock circuit for Interleaved mode operation is illustrated in Figure 16.
In Interleaved mode, both DACs use the same data and clock inputs at twice the update
rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A
or latch B, depending on the value of IQSEL. The IQSEL transition must occur when
IQWRT and IQCLK are LOW.
The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is
updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see Figure 17.
Fig 16. Interleaved mode
Fig 17. Interleaved mode timing
001aai824
÷ 2
14
14
DA13 to DA0
IQWRT
IQSEL
IQCLK
IQRESET
INPUT A
LATCH
DAC A
LATCH
14
14
INPUT B
LATCH
DAC B
LATCH
001aai940
DA13 to DA0/
DB13 to DB0
N N+1
XX
XX
N+1
N
N+3
N+5
N+2
N+4
N+2
IQRESET
IOUTAP, IOUTAN
IOUTBP, IOUTBN
N+3 N+4 N+5 N+6 N+7
IQSEL
IQWRT
IQCLK
DAC1401D125 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 17 of 25
Integrated Device Technology
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
10.3 Timing
The DAC1401D125 can operate at an update rate up to 125 Msps. This generates an
input data rate of 125 MHz in Dual port mode and 250 MHz in Interleaved mode. The
timing of the DAC1401D125 is shown in Figure 18.
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
• A configuration resulting in the same timing for the signals WRTA/WRTB and
CLKA/CLKB, can be achieved either by synchronizing them or by connecting them
together.
• The rising edge of the CLKA/CLKB signal can also be placed in a range from half a
period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns
after the rising edge of the WRTA/WRTB signal.
A typical set-up time of 0 ns and a hold time of 0.6 ns enable the DAC1405D125 to be
easily integrated into any application.
10.4 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
(1)
The output current depends on the digital input data:
Fig 18. Timing of the DAC1401D125
001aai937
t
su(i)
t
w(WRT)
DA13 to DA0/
DB13 to DB0
WRTA/
WRTB
CLKA/
CLKB
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
t
d(clk)
t
w(CLK)
10 %
90 %
t
d
t
t
t
s
t
h(i)
I
IOUTP
I
Ofs
DATA
16384
----------------


=
I
IOUTN
I
Ofs
16383 DATA–
16384
-----------------------------------------


=
DAC1401D125 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 18 of 25
Integrated Device Technology
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
Table 7 shows the output current as a function of the input data, when I
O(fs)
= 20 mA.
10.5 Full-scale current adjustment
The DAC1401D125 integrates one 1.25 V reference and two current sources to adjust the
full-scale current in both DACs.
The internal reference configuration is shown in Figure 19.
The bias current is generated by the output of the internal regulator connected to the
inverting input of the internal operational amplifiers. The external resistors R
A
and R
B
are
connected to pins AVIRES and BVIRES, respectively. This configuration is optimal for
temperature drift compensation because the bandgap can be matched with the voltage on
the feedback resistors.
The relationship between full-scale output current (I
O(fs)
) at the output of channel A or
channel B and the resistor is:
(2)
The output current of the two DACs is typically fixed at 20 mA when both resistors R
A
and
R
B
are set to 1.5 k. The operational range of DAC1401D125 is from 2 mA to 20 mA.
It is recommended to decouple pin REFIO using a 100 nF capacitor.
Table 7. DAC transfer function
Data DA13/DB13 to DA0/DB0 IOUTAP/IOUTBP IOUTAN/IOUTBN
0 00 0000 0000 0000 0 mA 20 mA
... ... ... ...
8192 10 0000 0000 0000 10 mA 10 mA
... ... ... ...
16383 11 1111 1111 1111 20 mA 0 mA
Fig 19. Internal reference configuration
001aai822
1.25 V REFERENCE
CURRENT
SOURCE
AGND
AGND
REFIO
AVIRES
BVIRES
R
A
CURRENT
SOURCE
AGND
R
B
100 nF
I
Ofs
24V
REFIO
R
A
------------------------
=
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DAC1401D125HL-C1

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IC DAC 14BIT A-OUT 48TQFP
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