AS7C3513B-12TCNTR

®
AS7C3513B
3/24/04, v.1.2 Alliance Semiconductor P. 4 of 10
Read cycle (over the operating range)
3,9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time
t
RC
10–12–1520–ns
Address access time
t
AA
10 12 15 20 ns 3
Chip enable (CE) access time
t
ACE
10 12 15 20 ns 3
Output enable (OE) access time
t
OE
–5–6–7–8ns
Output hold from address
change
t
OH
3–3–33–ns5
CE low to output in low Z
t
CLZ
3–3–33–ns4 , 5
CE high to output in high Z
t
CHZ
–3–3–4–5ns4 , 5
OE low to output in low Z
t
OLZ
0–0–00–ns4 , 5
Byte select access time
t
BA
–5–6–7–8ns
Byte select Low to low Z
t
BLZ
0–0–00–ns4 , 5
Byte select High to high Z
t
BHZ
–5–6–6–8ns4 , 5
OE high to output in high Z
t
OHZ
–5–6–7–8ns4 , 5
Power up time
t
PU
0–0–00–ns4 , 5
Power down time
t
PD
10 12 15 20 ns 4 , 5
Undefined output/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
Data OUT
Address
Data validPrevious data valid
®
AS7C3513B
3/24/04, v.1.2 Alliance Semiconductor P. 5 of 10
Read waveform 2 (CE, OE, UB, LB controlled)
3,6,8,9
Write cycle (over the operating range)
11
Parameter
Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time
t
WC
10 12 15 20 ns
Chip enable (CE) to write end
t
CW
8–9–10 12 ns
Address setup to write end
t
AW
8–9–10 12 ns
Address setup time
t
AS
0–0–0– 0 ns
Write pulse width
t
WP
7–8–9– 12 ns
Write recovery time
t
WR
0–0–0– 0 ns
Address hold from end of write
t
AH
0–0–0– 0 ns
Data valid to write end
t
DW
5–6–8– 10 ns
Data hold time
t
DH
0–0–0– 0 ns 5
Write enable to output in high
Z
t
WZ
–5–6–7 8 ns4 , 5
Output active from write end
t
OW
1–1–1– 2 ns4 , 5
Byte select low to end of write
t
BW
7–8–9– 9 ns
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data OUT
®
AS7C3513B
3/24/04, v.1.2 Alliance Semiconductor P. 6 of 10
Write waveform 1(WE controlled)
11
Write waveform 2 (CE controlled)
11
Address
LB
, UB
WE
Data IN
Data OUT
t
WC
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
Data undefined
High-Z
Data valid
t
WR
Address
CE
LB, UB
WE
Data IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data OUT
Data undefined
High-Z High-Z
t
AS
t
AW
Data valid
t
CLZ
t
WR
&

AS7C3513B-12TCNTR

Mfr. #:
Manufacturer:
Alliance Memory
Description:
SRAM 512K 3.3V 12ns FAST 32K x 16 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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