SY89421VZHC Datasheet SY89421VZC, SY89421VZHC | P1-P3

The SY89421V is a digital Phase Locked Loop based on

Micrel-Synergy's differential PLL technology. It is capable

of operating in the 30MHz to 560MHz reference input

frequency range, and up to 2000MHz with the HFIN input

and an external VCO. Use of a phase-frequency detector

results in excellent PLL locking and tracking characteristics.

Error correction voltages are generated by the detector if

either phase or frequency deviations occur. The VCO has

a frequency range covering more than a 2:1 ratio from

480MHz to 1120MHz.

Feedback for the loop is realized by connecting FOUT,

FOUT to FIN, FIN by means of external circuitry. This

allows the flexibility of inserting additional circuitry off-chip

in the feedback paths, such as an additional divider and/or

buffer. Pulldown resistors are required for the FOUT and

FOUT pins. High frequency inputs HFIN, HFIN and

corresponding outputs HFOUT, HFOUT are featured for

use with external components such as an active loop filter

and a high frequency VCO.

Select pins S1 and S2 are used to program the N divider

for optimum VCO operation, in other words with the VCO in

the center of its range. Select pin S3 allows bypassing the

N divider enabling the PLL to output the VCO directly.

Select pin S4 is used to select off-chip or on-chip VCO.

Select pin S5 enables the divide-by-two prescaler, which is

useful in frequency doubling applications. All Select pins

are TTL compatible.

FEATURES

■ 3.3V and 5V power supply options

■ 1.12GHz maximum VCO frequency

■ 30MHz to 560MHz reference input operating

frequency

■ External 2.0GHz VCO capability

■ Low jitter differential design

■ Frequency doubler mode

■ PECL Differential output

■ External loop filter optimizes performance/cost

■ Available in 20-pin SOIC package

DESCRIPTION

ClockWorks™

SY89421V

FINAL

5V/3.3V

HIGH-PERFORMANCE

PHASE LOCKED LOOP

APPLICATIONS

■ Workstations

■ Advanced communications

■ High-performance computing

PIN CONFIGURATION

TOP VIEW

SOIC

Z20-1

FIN

HFIN

HFOUT

CCO

FOUT

RIN

Rev.: F Amendment: /0

Issue Date: May 2000

ClockWorks™

SY89421V

Micrel

BLOCK DIAGRAM

LOOP FILTER COMPONENT SELECTION

C = 1.0µF ±10% (X7R dielectric)

R = 560Ω ±10%

F1 F2

RIN

F1 F2

VCO

FIN

FOUT

÷ P

(1, 2)

HFOUT

HFIN

÷ 2

MUX

LOOP

FILTER

PHASE-FREQUENCY

DETECTOR

÷ N

(1,2,4,8,10,12,16,20)

ClockWorks™

SY89421V

Micrel

Pin Function I/O

F1 Filter Pin 1 I/O

F2 Filter Pin 2 I/O

RIN Reference Input I

RIN Inverted Reference Input I

FIN Feedback Input I

FIN Inverted Feeback Input I

HFIN High Frequency Input I

HFIN Inverted High Frequency Input I

HFOUT High Frequency Output O

HFOUT Inverted High Frequency Output O

FOUT Frequency Output O

FOUT Inverted Frequency Output O

VCC VCC —

VCCO Output VCC —

VEE VEE (0V) —

S1 Select Input 1 (TTL) I

S2 Select Input 2 (TTL) I

S3 Select Input 3 (TTL) I

S4 Select Input 4 (TTL) I

S5 Select Input 5 (TTL) I

RIN, RIN

Reference frequency inputs. These are differential signal

pairs and may be driven differentially or single-ended.

FIN, FIN

Feedback frequency inputs. These are a differential signal

pair and may be driven differentially or single-ended.

HFIN, HFIN

High frequency feedback inputs. These are a differential

signal pair. Differential drive is recommended.

F1, F2

These pins are connection points for the loop filter, which is to

be provided off-chip. F1 is the high impedance side, F2 is the

reference side. The loop filter should be a first order, low pass

with a DC block. The difference voltage on these pins will be

a dc level, which is controlled by the loop feedback and

determined by the required VCO frequency.

FOUT, FOUT

Frequency outputs for the loops. These are differential, positive

referenced, emitter-follower signals and must be terminated

off chip. Termination in 50 ohms is recommended.

HFOUT, HFOUT

High frequency output. These are a differential signal pair.

Termination in 50 ohms is recommended.

S1, S2, S3, S4, S5

These are the frequency select inputs, and are used to

configure the PLL. They are compatible with standard TTL

signal levels. See the Frequency Selection Table for details

of the logic.

VCC

This is the positive supply for the chip. It should be decoupled

and should present a very low impedance in order to assure

low-jitter operation.

VCCO

This is the positive supply for the output buffer. It is constrained

to be equal to or less than the value of VCC. It should be

decoupled and should present a very low impedance for low-

jitter.

VEE

This pin is the negative supply for the chip and is normally

connected to ground (0V).

PIN NAMES PIN DESCRIPTION

P1-P3 P4-P6 P7-P8

SY89421VZHC

Mfr. #:

Buy SY89421VZHC

Manufacturer:

Description:

IC PHASE LOCK LOOP 5/3.3V 20SOIC

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SY89421VZHC

SY89421VZHC

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