NCP1093, NCP1094
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Table 1. PIN DESCRIPTION
Name
Pin No.
Type Description
NCP1093 NCP1094
INRUSH 1 1 Output Current limit programming pin. Connect a resistor between INRUSH and
VPORTN.
CLASS 2 2 Output Classification current programming pin. Connect a resistor between CLASS
and VPORTN.
DET 3 3 Output,
Open Drain
Detection pin. Connect a 24.9 kW resistor between DET and VPORTP for a
valid PD detection signature.
VPORTN1 4 4 Ground Negative input power. Connected to the source of the internal pass−switch
VPORTN2 5 5 Ground Negative input power. Connected to the source of the internal pass−switch
RTN 6 6 Ground DC−DC controller power return. Connected to the drain of the internal pass−
switch
PGOOD 7 7 Output,
Open Drain
Open Drain Power Good Indicator. Pin is in HZ mode when the power good
signal is active.
UVLO 8 − Input Undervoltage lockout input. Voltage with respect to VPORTN. Connect a resist-
or−divider from VPORTP to UVLO to VPORTNx to set an external UVLO
threshold.
AUX − 8 Input Auxiliary Pin. When this pin is pulled up, the Pass Switch is disabled and allows
a supply transition from PSE to the rear auxiliary supply connected between
VPORTP and RTN.
NCLASS_AT 9 9 Output Active low enable signal used to verify high power operation
VPORTP 10 10 Input Positive input power. Voltage with respect to VPORTN.
Exposed Pad EP EP Ground Exposed pad should be connected to VPORTN.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Units Conditions
VPORTP Input power supply −0.3 72 V Voltage with respect to VPORTN
RTN Analog ground supply 2 −0.3 72 V Pass−switch in off−state (voltage with respect to VPORTN)
CLASS Analog output −0.3 72 V Voltage with respect to VPORTN
INRUSH Analog output −0.3 3.6 V Voltage with respect to VPORTN
AUX Analog input −0.3 72 V Voltage with respect to VPORTN
UVLO Analog input −0.3 3.6 V Voltage with respect to VPORTN
PGOOD Analog output −0.3 72 V Voltage with respect to RTN
T
A
Ambient temperature −40 85 °C
T
J
Junction temperature − 125 °C
T
J
, T
SD
Junction temperature
(Note 1)
− 175 °C Thermal shutdown condition
T
STG
Storage Temperature −55 150 °C
T
q
JA
Thermal Resistance,
Junction to Air (Note 2)
50 °C/W DFN−10
ESD−HBM Human Body Model 2 kV per EIA−JESD22−A114 standard
ESD−CDM Charged Device Model 500 V per ESD−STM5.3.1 standard
ESD−MM Machine Model 200 V per EIA−JESD22−A115−A standard
LU Latch−up ±100 mA per JEDEC Standard JESD78
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. Low q JA is obtained with 2S2P test board (2 signal − 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural
convection. Refer to Jedec JESD51 for details. The exposed pad must be connected to the VPORTN ground pin.
