MC74HCT541AFG

© Semiconductor Components Industries, LLC, 2014
June, 2017 − Rev. 8
1 Publication Order Number:
MC74HCT541A/D
MC74HCT541A
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.
The HCT541A is an octal non−inverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
Features
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
Output
Enables
Data
Inputs
Non-Inverting
Outputs
PIN 20 = V
CC
PIN 10 = GND
LOGIC DIAGRAM
www.onsemi.com
See detailed ordering and shipping information on page 4 o
f
this data sheet.
ORDERING INFORMATION
1
20
MARKING DIAGRAMS
SOIC−20
DW SUFFIX
CASE 751D
HCT541A
AWLYYWWG
HCT
541A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20 TSSOP−20
PIN ASSIGNMENT
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1 OE2 A
L
H
Z
Z
Z = High Impedance
X = Don’t Care
MC74HCT541A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air SOIC Package† 500 mW
T
stg
Storage Temperature Range –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC Package)
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
V
in
, V
out
DC Input Voltage, Output Voltage
(Referenced to GND)
0 V
CC
V
T
A
Operating Temperature Range, All Package Types –55 +125
_C
t
r
, t
f
Input Rise/Fall Time (Figure 1) 0 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
V
Guaranteed Limit
Symbol Parameter Condition −55 to 25°C 85°C 125°C Unit
V
IH
Minimum High−Level Input Voltage V
out
= 0.1V or V
CC
− 0.1V
|I
out
| 20mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input Voltage V
out
= 0.1V or V
CC
− 0.1V
|I
out
| 20mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High−Level Output Voltage V
in
= V
IH
or V
IL
|I
out
| 20mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IH
or V
IL
|I
out
| 6.0mA 4.5 3.98 3.84 3.70
V
OL
Maximum Low−Level Output Voltage V
in
= V
IH
or V
IL
|I
out
| 20mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 6.0mA 4.5 0.26 0.33 0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 5.5 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum 3−State Leakage Current Output in High Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ±0.5 ±5.0 ±10.0
mA
I
CC
Maximum Quiescent Supply Current
(per Package)
V
in
= V
CC
or GND
I
out
= 0mA
5.5 4 40 160
mA
DI
CC
Additional Quiescent Supply Current V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
5.5
−55°C 25 to 125°C
mA
2.9 2.4
1. Total Supply Current = I
CC
+ ΣDI
CC
.
This device contains protection
circuitry to guard against damage due
to high static voltages or electric
fields. However, precautions must be
taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be tied
to an appropriate logic voltage level
(e.g., either GND or V
CC
). Unused
outputs must be left open.
MC74HCT541A
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3
AC CHARACTERISTICS (V
CC
= 5.0V, C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol Parameter −55 to 25°C 85°C 125°C Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
23 28 32 ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
30 34 38 ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
30 34 38 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
12 15 18 ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum 3−State Output Capacitance (Output in High Impedance State) 15 15 15 pF
C
PD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25°C, V
CC
= 5.0 V
pF
55
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
Figure 1.
C
L
*
*Includes all probe and jig capacitance
TEST
POINT
OE1 or OE2
1.3V
3.0V
GND
OUTPUT Y
t
PZL
OUTPUT Y
t
PZH
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
10%
90%
t
PLZ
t
PHZ
1.3V
1.3V
Figure 2.
SWITCHING WAVEFORMS
DEVICE
UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 3. Figure 4.
C
L
*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
1kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
and t
PZH
.
3.0V
GND
INPUT A
OUTPUT Y
t
PLH
t
PHL
90%
1.3V
10%
t
r
t
TLH
t
f
t
THL
90%
1.3V
10%
1.3V

MC74HCT541AFG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 5V Octal 3-State Non-Inverting TTL
Lifecycle:
New from this manufacturer.
Delivery:
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