CYV270M0104EQ-LXC

CYV270M0104EQ
Adaptive Video Cable Equalizer
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-12875 Rev. ** Revised October 25, 2007
Features
Adaptive cable equalization
SMPTE 259M Compliant
Supports DVB-ASI at 270 Mbps
Multi standard operation from 143 Mbps to 360 Mbps
Maximum cable length adjustment
Carrier detect and mute functionality
Equalizer bypass mode
Seamless connection with HOTLink II™ Family and HOTLink
®
Receiver
Equalizes up to 350m of Belden 1694A and Canare L-5CFB
coaxial cable at 270 Mbps
Low power: 160 mW at 3.3V
Single 3.3V supply
16-pin Quad Flat Pb-free (QFN) package
0.18 μm CMOS technology
Pb-free and RoHS compliant
Pin compatible to existing QFN equalizer devices
Uses Cypress CLEANLink™ technology
Functional Description
The CYV270M0104EQ is an adaptive video cable equalizer
designed to equalize and restore signals received over 75Ω
coaxial cable. The equalizer is designed to meet SMPTE 259M
data rates and is optimized for performance at 270 Mbps. The
CYV270M0104EQ is optimized to equalize up to 350m of Belden
1694A and Canare L-5CFB coaxial cable at 270 Mbps. The
CYV270M0104EQ connects seamlessly to the HOTLink II family
of transceiver devices and HOTLink receiver devices.
The CYV270M0104EQ has DC restoration to compensate for
the DC content of the SMPTE pathological patterns. The
maximum cable length adjust (MCLADJ) sets the approximate
maximum cable length to equalize. The CYV270M0104EQ’s
differential serial outputs (SDO, SDO
) mute, when the approx-
imate cable length set by MCLADJ is reached and carrier detect
(CD) is tied to MUTE. The MUTE pin controls muting of the
equalizer outputs.
Power consumption is typically 160 mW at 3.3V.
Serial Links
Copper Cable
CYV270M0104EQ
Connections
Equalizer System Connection Diagram
Cable
Driver
HOTLink II
Serializer
HOTLink II
Deserializer
Adaptive
Cable
Equalizer
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CYV270M0104EQ
Document Number: 001-12875 Rev. ** Page 2 of 9
Pinouts
Figure 1. Pin Diagram - 16 Pin QFN (Top View)
CYV270M0104EQ Adaptive Video Cable Equalizer Block Diagram
CYV270M0104EQ Adaptive Video Cable Equalizer Block Diagram
Differential Output
Cable Length Analog
Adjustor and Mute
Threshold Block
Carrier Detect and
Mute Control Block
DC Restore
Equalizer
MUTE
BYPASS
SDO, SDO
SDI, SDI
MCLADJ
CD
2
3
4
5678
SDO
GND
MCLADJ
BYPASS
SDI
AGC
GND
SDI
SDO
GND
AGC
GND
VCC
MUTE
VCC
CD
Center Pad
(bottom of package)
1
16 15 14 13
11
10
9
12
CYV270M0104EQ
(Marked CY01EQ
On Package)
Equalizer Block Diagram
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CYV270M0104EQ
Document Number: 001-12875 Rev. ** Page 3 of 9
Table 1. Pin Descriptions - CYV270M0104EQ Adaptive Video Cable Equalizer
Name IO Characteristics Signal Description
Control Signals
MUTE LVTTL Input Mute. When the MUTE pin is set LOW, the equalizer’s differential serial outputs are not
muted.
When the MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted. The
BYPASS setting is ignored when MUTE is HIGH.
Connecting CD
to the MUTE pin enables automatic muting of the equalizer when the signal
is lost.
Do not leave an unused MUTE pin floating. Always drive it to a known state.
CD LVTTL Output Carrier Detect. When the incoming data stream is present and maximum cable length set
by MCLADJ is not exceeded, CD
outputs a voltage less than 0.8V.
When the incoming data stream is not present or maximum cable length set by MCLADJ
is exceeded, CD
outputs a voltage greater than 2.8V.
Connecting CD
to the MUTE pin enables automatic muting of the equalizer when the signal
is lost.
MCLADJ Analog Input Maximum Cable Length Adjust. The maximum cable length to equalize is set by the
voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ is
reached, the CD
indicator deasserts.
If MCLADJ functionality is not required, then this pin should be left floating or tied to ground
to allow maximum equalized cable length.
BYPASS LVTTL Input Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer’s
differential serial inputs (SDI, SDI
) is routed to the equalizer’s differential serial outputs
(SDO, SDO
) without performing equalization.
When BYPASS is set LOW, the incoming video data stream is equalized and presented
at the equalizer‘s serial differential outputs (SDO, SDO
).
When MUTE is set HIGH, the BYPASS setting is ignored and the serial outputs are muted.
AGC, AGC Analog Automatic Gain Control. Place a 1 μF capacitor between the AGC and AGC pins.
SDO, SDO Differential
Output
Differential Serial Outputs. The equalized serial video data stream is presented at the
SDO/SDO
differential serial CML output.
SDI, SDI Differential
Input
Differential Serial Inputs. SDI/SDI accepts either a single-ended or differential serial
video data stream over 75Ω coaxial cable.
Power
VCC Power Power Supply for Device. Connect to +3.3V DC.
GND Gnd Connect to Ground.
Center Pad Connect to PCB Ground for Maximum Thermal Dissipation.
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CYV270M0104EQ-LXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Equalizers Multi-Format HD/SD Video Equalizer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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