12
LT1107
1107fa
Figure 7 details current limit circuitry. Sense transistor A1,
whose base and emitter are paralleled with power switch
Q2, is ratioed such that approximately 0.5% of Q2’s
collector current flows in Q1’s collector. This current is
passed through internal 80Ω resistor R1 and out through
the I
LIM
pin. The value of the external resistor connected
between I
LIM
and V
IN
sets the current limit. When suffi-
cient switch current flows to develop a V
BE
across R1 +
R
LIM
, Q3 turns on and injects current into the oscillator,
turning off the switch. Delay through this circuitry is
approximately 800ns. The current trip point becomes less
accurate for switch ON times less than 3µs. Resistor
values programming switch ON time for 800ns or less will
cause spurious response in the switch circuitry although
the device will still maintain output regulation.
Using the Gain Block
The gain block (GB) on the LT1107 can be used as an error
amplifier, low-battery detector or linear post regulator.
The gain block itself is a very simple PNP input op amp with
an open collector NPN output. The negative input of the
gain block is tied internally to the 1.25V reference. The
positive input comes out on the SET pin.
Arrangement of the gain block as a low-battery detector is
straightforward. Figure 8 shows hookup. R1 and R2 need
only be low enough in value so that the bias current of the
SET input does not cause large errors. 33k for R2 is
adequate. R3 can be added to introduce a small amount of
hysteresis. This will cause the gain block to “snap” when
the trip point is reached. Values in the 1M to 10M range are
optimal. The addition of R3 will change the trip point,
however.
Output ripple of the LT1107, normally 50mV at 5V
OUT
can
be reduced significantly by placing the gain block in front
of the FB input as shown in Figure 9. This effectively
reduces the comparator hysteresis by the gain of the gain
block. Output ripple can be reduced to just a few millivolts
using this technique. Ripple reduction works with step-
down or inverting modes as well. For this technique to be
effective, output capacitor C1 must be large, so that each
switching cycle increases V
OUT
by only a few millivolts.
1000µF is a good starting value. C1 should be a low ESR
type as well.
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
1107 F07
SW2
SW1
DRIVER
OSCILLATOR
V
IN
I
LIM
R1
80Ω
(INTERNAL)
R
LIM
(EXTERNAL)
Q3
Q2
Q1
Figure 7. LT1107 Current Limit Circuitry
L1
1107 F09
D1
R3
270k
V
OUT
R2
R1
C1
V
BAT
LT1107
GND SW2
SET
SW1
I
LIM
V
IN
FB
AO
V
OUT
= +1 1.25V
R2
R1
()()
+
Figure 9. Output Ripple Reduction Using Gain Block
Figure 8. Setting Low-Battery Detector Trip Point
1107 F08
V
BAT
R1
R2
1.25V
REF
SET
GND
V
IN
LT1107
47k
5V
TO
PROCESSOR
AO
R3
R1 =
V
LB
= BATTERY TRIP POINT
R2 = 33k
R3 = 1.6M
()
V
LB
– 1.25V
35.1µA
+
–
