4
Transmitter and Receiver Signaling Rate Range and
BER Performance
For purposes of de nition, the symbol rate (Baud), also
called signaling rate, is the reciprocal of the symbol time.
Data rate (bits/sec) is the symbol rate divided by the
encoding factor used to encode the data (symbols/bit).
The speci cations in this data sheet have all been
measured using the standard Fibre Channel symbol rate
of 266 MBd.
The data link modules can be used for other applica-
tions at signaling rates di erent than speci ed in this
data sheet. Depending on the actual signaling rate, there
may be some di erences in optical power budget. This is
primarily caused by a change in receiver sensitivity.
These data link modules can also be used for applications
which require di erent bit-error-ratio (BER) performance.
Figure 5 illustrates the typical trade-o between link BER
and the receiver input optical power level.
Data Link Jitter Performance
The Avago 1300 nm data link modules are designed to
operate per the system jitter allocations stated in FC-PH
Annex A.4.3 and A.4.4.
The 1300 nm transmitter will tolerate the worst-case input
electrical jitter allowed, without violating the worst-case
output jitter requirements.
The 1300 nm receiver will tolerate the worst-case input
optical jitter allowed without violating the worst-case
output electrical jitter allowed.
The jitter speci cations stated in the following transmitter
and receiver speci cation tables are derived from the
values in FC-PH Annex A.4.3 and A.4.4. They represent
the worst-case jitter contribution that the transmitter and
receiver are allowed to make to the overall system jitter
without violating the allowed allocation. In practice, the
typical jitter contribution of the Avago data link modules
is well below the maximum allowed amounts.
Recommended Handling Precautions
It is advised that normal static precautions be taken in
the handling and assembly of these data link modules to
prevent damage which may be induced by electrostatic
discharge (ESD). The HFBR-1119TZ/-2119TZ series meets
MIL-STD-883C Method 3015.4 Class 2.
Care should be taken to avoid shorting the receiver Data
or Signal Detect Outputs directly to ground without
proper currentlimiting impedance.
Solder and Wash Process Compatibility
The transmitter and receiver are delivered with protec-
tive process caps covering the individual ST* ports. These
process caps protect the optical subassemblies during
wave solder and aqueous wash processing and act as dust
covers during shipping.
These data link modules are compatible with either
industry standard wave- or hand-solder processes.
Shipping Container
The data link modules are packaged in a shipping
container designed to protect it from mechanical and ESD
damage during shipment or storage.
Board Layout – Interface Circuit and Layout Guidelines
It is important to take care in the layout of your circuit
board to achieve optimum performance from these data
link modules. Figure 6 provides a good example of a
power supply lter circuit that works well with these parts.
Also, suggested signal terminations for the Data, Data-bar,
Signal Detect and Signal Detect-bar lines are shown. Use
of a multilayer, ground-plane printed circuit board will
provide good high-frequency circuit performance with
a low inductance ground return path. See additional
recommendations noted in the interface schematic
shown in Figure 6.
Figure 5. HFBR-1119TZ/2119TZ bit-error-ratio vs. relative receiver input
optical power.
BIT ERROR RATIO
RELATIVE INPUT OPTICAL POWER – dB
1 x 10
-8
1 x 10
-10
-4
1 x 10
-2
-2
1 x 10
-12
1 x 10
-6
26-0
1 x 10
-11
1 x 10
-9
1 x 10
-7
1 x 10
-5
1 x 10
-3
1 x 10
-4
CONDITIONS:
1. 266 MBd
2. PRBS 2
7
-1
3. T
A
= 25 °C
4. V
CC
= 5 Vdc
5. INPUT OPTICAL RISE/FALL TIMES =
1.0/1.9 ns
CENTER OF SYMBOL
