NCD5701A, NCD5701B, NCD5701C
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Table 1. PIN FUNCTION DESCRIPTION
Pin Name No. I/O/x Description
VIN 1 I Input signal to control the output. In applications which require galvanic isolation, VIN is generat-
ed at the opto output, the pulse transformer secondary or the digital isolator output. There is a
signal inversion from VIN to VO (VOH/VOL). VIN is internally clamped to 5.5 V and has a pull−
up resistor of 1 MW to ensure that an output is low in the absence of an input signal. A minimum
pulse−width is required at VIN before VO (VOH/VOL) is activated.
VREF 2 O 5 V Reference generated within the driver is brought out to this pin for external bypassing and
for powering low bias circuits (such as digital isolators).
FLT 3 O Fault output (active low) that allows communication to the main controller that the driver has
encountered a fault condition and has deactivated the output. Capable of driving optos or digital
isolators when isolation is required. (Truth Table is provided in the datasheet to indicate condi-
tions under which this signal is asserted.)
DESAT 4 I Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to
this pin allows a programmable blanking delay every ON cycle before DESAT fault is processed,
thus preventing false triggering.
VCC 5 x Positive bias supply for the driver. The operating range for this pin is from UVLO to the maxi-
mum. A good quality bypassing capacitor is required from this pin to GND and should be placed
close to the pins for best results.
VO
(NCD5701A,
NCD5701B)
6 O Driver output that provides the appropriate drive voltage, source and sink current to the IGBT
gate. VO is actively pulled low during start−up and under Fault conditions.
VOH
(NCD5701C)
6 O Driver high output that provides the appropriate drive voltage and source current to the IGBT
gate.
VOL
(NCD5701C)
7 O Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate.
VOL is actively pulled low during start−up and under Fault conditions.
GND
(NCD5701A,
NCD5701B)
7 x This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.
GND
(NCD5701C)
8 x This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors
should be referenced to this pin and kept at a short distance from the pin.
VEE
(NCD5701B)
8 x A negative voltage with respect to GND can be applied to this pin and that will allow VO to go to
a negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to
GND. If a negative voltage is not applied or available, this pin must be connected to GND.
CLAMP
(NCD5701A)
8 I/O Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To
be tied directly to IGBT gate with minimum trace length for best results.
