6.42
16
IDT71V2557, IDT71V2559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 2.5V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and
voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions
(0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V).
5. Commercial temperature range only.
7.5ns
(5)
8ns 8.5ns
t
CY C
Clock Cycle Time 10
____
10.5
____
11
____
ns
t
CH
(1)
Clock High Pulse Width 2.5
____
2.7
____
3.0
____
ns
t
CL
(1)
Clock Low Pulse Width 2.5
____
2.7
____
3.0
____
ns
t
CD
Clock High to Valid Data
____
7.5
____
8
____
8.5 ns
t
CDC
Clock High to Data Change 2
____
2
____
2
____
ns
t
CL Z
(2, 3 ,4 )
Clock High to Output Active 3
____
3
____
3
____
ns
t
CHZ
(2, 3 ,4 )
Clock High to Data High-Z
____
5
____
5
____
5ns
t
OE
Output Enable Access Time
____
5
____
5
____
5ns
t
OLZ
(2,3)
Output Enable Low to Data Active 0
____
0
____
0
____
ns
t
OHZ
(2,3)
Output Enable High to Data High-Z
____
5
____
5
____
5ns
t
SE
Clock Enable Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SA
Address Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SD
Data In Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SW
Read/Write (R/W) Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SADV
Advance/Load (ADV/LD) Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SC
Chip Enable/Select Setup Time 2.0
____
2.0
____
2.0
____
ns
t
SB
Byte Write Enable (BWx) Setup Time 2.0
____
2.0
____
2.0
____
ns
t
HE
Clock Enable Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HW
Read/Write (R/W) Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HADV
Advance/Load (ADV/LD) Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write Enable (BWx) Hold Time 0.5
____
0.5
____
0.5
____
ns
4878 tbl 24