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CY7C025AV-20AXI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 10 of 19
Data Retention Mode
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV are designed for battery backup.
Data retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within V
CC
to V
CC
– 0.2V.
2. CE
must be kept between V
CC
– 0.2V and 70 percent of V
CC
during the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (3.0V).
Notes
25. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
26. Test conditions used are Load 2.
27. t
BDD
is a calculated parameter and is the greater of t
WDD
– t
PWE
(actual) or t
DDD
– t
SD
(actual).
28. CE
= V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
t
PWE
Write Pulse Width 15 20 ns
t
SD
Data Setup to Write End 15 15 ns
t
HD
Data Hold From Write End 0 0 ns
t
HZWE
[23, 24]
R/W LOW to High Z 12 15 ns
t
LZWE
[23, 24]
R/W HIGH to Low Z 3 0 ns
t
WDD
[25]
Write Pulse to Data Delay 45 50 ns
t
DDD
[25]
Write Data Valid to Read Data Valid 30 35 ns
Busy Timing
[26]
t
BLA
BUSY LOW from Address Match 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch 20 20 ns
t
BLC
BUSY LOW from CE LOW 20 20 ns
t
BHC
BUSY HIGH from CE HIGH 17 17 ns
t
PS
Port Setup for Priority 5 5 ns
t
WB
R/W HIGH after BUSY (Slave) 0 0 ns
t
WH
R/W HIGH after BUSY HIGH (Slave) 15 17 ns
t
BDD
[27]
BUSY HIGH to Data Valid 20 25 ns
Interrupt Timing
[26]
t
INS
INT Set Time 20 20 ns
t
INR
INT Reset Time 20 20 ns
Semaphore Timing
t
SOP
SEM Flag Update Pulse (OE or SEM)1012ns
t
SWRD
SEM Flag Write to Read Time 5 5 ns
t
SPS
SEM Flag Contention Window 5 5 ns
t
SAA
SEM Address Access Time 20 25 ns
Switching Characteristics
Over the Operating Range (continued)
[20]
Parameter Description
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Unit
-20 -25
Min Max Min Max
Timing
Parameter Test Conditions
[28]
Max Unit
ICC
DR1
at VCC
DR
= 2V 50 μA
Data Retention Mode
3.0V
3.0V
V
CC
> 2.0V
V
CC
to V
CC
– 0.2V
V
CC
CE
t
RC
V
IH
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 11 of 19
Switching Waveforms
Notes
29. R/W
is HIGH for read cycles.
30. Device is continuously selected CE
= V
IL
and UB or LB = V
IL
. This waveform cannot be used for semaphore reads.
31. OE
= V
IL
.
32. Address valid prior to or coincident with CE
transition LOW.
33. To access RAM, CE
= V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CE = V
IH
, SEM = V
IL
.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
OHA
Figure 5. Read Cycle No. 1 (Either Port Address Access)
[29, 30, 31]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
t
LZCE
t
PU
t
PD
I
SB
I
CC
DATA OUT
OE
CE and
LB
or UB
CURRENT
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)
[29, 32, 33]
UB or LB
DATA OUT
t
RC
ADDRESS
t
AA
t
OHA
CE
t
LZCE
t
ABE
t
HZCE
t
HZCE
t
ACE
t
LZCE
Figure 7. Read Cycle No. 3 (Either Port)
[29, 31, 32, 33]
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J Page 12 of 19
Notes
34. R/W
or CE must be HIGH during all address transitions.
35. A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM and a LOW UB or LB.
36. t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
37. If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to enable the IO drivers to turn off and
data to be placed on the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
PWE
.
38. To access RAM, CE
= V
IL
, SEM = V
IH
.
39. To access upper byte, CE
= V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE
= V
IL
, LB = V
IL
, SEM = V
IH
.
40. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.
41. During this period, the IO pins are in the output state, and input signals must not be applied.
42. If the CE
or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Figure 8. Write Cycle No. 1: R/W Controlled Timing
[34, 35, 36, 37]
[40]
[40]
[37]
[38, 39]
NOTE 41
NOTE 41
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Figure 9. Write Cycle No. 2: CE Controlled Timing
[34, 35, 36, 42]
[38, 39]
[+] Feedback
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY7C025AV-20AXI

Mfr. #:
Buy CY7C025AV-20AXI
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 128K PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
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