SM560
Document #: 38-07020 Rev. *E Page 4 of 8
Absolute Maximum Ratings
[1]
Supply Voltage (V
DD
): .................................... –0.5V to +6.0V
DC Input Voltage:..................................–0.5V to VDD + 0.5V
Junction Temperature .................................–40°C to +140°C
Operating Temperature:...................................... 0°C to 70°C
Storage Temperature.................................. –65°C to +150°C
Static Discharge Voltage (ESD).......................... 2,000V-Min.
SSCG Theory of Operation
The SM560 is a PLL-type clock generator using a proprietary
Cypress design. By precisely controlling the bandwidth of the
output clock, the SM560 becomes a Low EMI clock generator.
The theory and detailed operation of the SM560 will be
discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50-duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda
-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse
-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda
-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multi-layer PCBs, etc. The SM560 uses the approach of
reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The SM560 takes a narrow band
digital reference clock in the range of 25–108 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand
what happens to a clock when SSCG is applied, consider a
65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
know the following:
Note:
1. Single Power Supply: The Voltage on any input or I/O pin cannot exceed the power pin during power up.
Table 2. DC Electrical Characteristics: V
DD
= 3.3V, Temp. = 25°C and C
L
(Pin 4) = 15 pF, unless otherwise noted
Parameter Description Conditions Min. Typ. Max. Unit
V
DD
Power Supply Range ±10% 2.97 3.3 3.63 V
V
INH
Input High Voltage S0 and S1 only 0.85V
DD
V
DD
V
DD
V
V
INM
Input Middle Voltage S0 and S1 only 0.40V
DD
0.50V
DD
0.60V
DD
V
V
INL
Input Low Voltage S0 and S1 only 0.0 0.0 0.15V
DD
V
V
OH1
Output High Voltage I
OH
= 6 mA 2.4 V
V
OH2
Output High Voltage I
OH
= 20 mA 2.0 V
V
OL1
Output Low Voltage I
OH
= 6 mA 0.4 V
V
OL2
Output Low Voltage I
OH
= 20 mA 1.2 V
Cin1 Input Capacitance Xin/CLK (Pin 1) 3 4 5 pF
Cin2 Input Capacitance Xout (Pin 8) 6 8 10 pF
Cin2 Input Capacitance S0, S1, SSCC (Pins 7,6,5) 3 4 5 pF
I
DD1
Power Supply Current F
IN
= 40 MHz 30 40 mA
I
DD2
Power Supply Current F
IN
= 65 MHz 35 45 mA
Table 3. Electrical Timing Characteristics: V
DD
= 3.3V, T = 25°C and C
L
= 15 pF, unless otherwise noted
Parameter Description Conditions Min. Typ. Max. Unit
ICLKFR Input Clock Frequency Range V
DD
= 3.30V 25 108 MHz
Trise Clock Rise Time (Pin 4) SSCLK1 @ 0.4 – 2.4V 1.2 1.4 1.6 ns
Tfall Clock Fall Time (Pin 4) SSCLK1 @ 0.4 – 2.4V 1.2 1.4 1.6 ns
DTYin Input Clock Duty Cycle XIN/CLK (Pin 1) 20 50 80 %
DTYout Output Clock Duty Cycle SSCLK1 (Pin 4) 45 50 55 %
JCC Cycle-to-Cycle Jitter Fin = 25 – 108 MHz - 125 175 ps
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