MAX4397SCTM+T Datasheet MAX4397SCTM+, MAX4397SCTM+T | P16-P18

MAX4397

Volume Control

The TV channel volume control ranges from -56dB to

+6dB in 2dB steps. The VCR volume control settings

are programmable for -6dB, 0dB, and +6dB. These

gain levels are referenced to the application inputs,

where some dividers are present. With the ZCD bit set,

the TV volume control switches only at zero-crossings,

thus minimizing click noise. The TV outputs can bypass

the volume control. Likewise, the monaural output sig-

nal can be processed by the TV volume control or it

can bypass the volume control.

Digital Section

Serial Interface

The MAX4397 uses a simple 2-wire serial interface

requiring only two standard microprocessor port I/O

lines. The fast-mode I

C-compatible serial interface

allows communication at data rates up to 400kbps or

400kHz. Figure 6 shows the timing diagram of the sig-

nals on the 2-wire interface.

The two bus lines (SDA and SCL) must be at logic-high

when the bus is not in use. The MAX4397 is a slave

device and must be controlled by a master device.

Pullup resistors from the bus lines to the supply are

required when push-pull circuitry is not driving the

lines.

The logic level on the SDA line can only change when

the SCL line is low. The start and stop conditions occur

when SDA toggles low/high while the SCL line is high

(see Figure 6). Data on SDA must be stable for the

duration of the setup time (t

SU,DAT

) before SCL goes

high. Data on SDA is sampled when SCL toggles high

with data on SDA stable for the duration of the hold time

HD,DAT

). Note that data is transmitted in an 8-bit byte.

A total of nine clock cycles are required to transfer a

byte to the MAX4397. The device acknowledges the

successful receipt of the byte by pulling the SDA line

low during the 9th clock cycle.

Audio/Video Switch for Dual SCART Connectors

16 ______________________________________________________________________________________

SCL

SDA

LOW

STA

DAT

STA

DAT

STA

BUF

STA

STOP CONDITIONREPEATED START CONDITIONSTART CONDITION

Figure 6. SDA and SCL Signal Timing Diagram

Data Format of the I

C Interface

C Compatibility

The MAX4397 is compatible with existing I

C systems.

SCL and SDA are high-impedance inputs. SDA has an

open drain that pulls the bus line to a logic-low during

the 9th clock pulse. Figure 7 shows a typical I

C inter-

face application. The communication protocol supports

the standard I

C 8-bit communications. The MAX4397

address is compatible with the 7-bit I

C addressing

protocol only; 10-bit format is not supported.

Digital Inputs and Interface Logic

The I

C-compatible, 2-wire interface has logic levels

defined as V

= 0.8V and V

= 2.0V. All of the inputs

include Schmitt-trigger buffers to accept low-transition

interfaces. The digital inputs are compatible with 3V

CMOS logic levels.

Programming

Connect DEV_ADDR to ground to set the MAX4397

write and read address as shown in Table 2.

Data Register Writing and Reading

Program the SCART video and audio switches by writ-

ing to registers 00h through 0Dh. Registers 00h through

0Eh can also be read, allowing read-back of data after

programming and facilitating system debugging. The

status register is read-only and can be read from

address 0Eh. See Tables 3–12 for register program-

ming information.

Applications Information

Hot-Plug of SCART Connectors

The MAX4397 features high-ESD protection on all

SCART inputs and outputs, and requires no external

transient-voltage suppressor (TVS) devices to protect

against floating chassis discharge. Some set-top boxes

have a floating chassis problem in which the chassis is

not connected to earth ground. As a result, the chassis

can charge up to 500V. When a SCART cable is con-

nected to the SCART connector, the charged chassis

can discharge through a signal pin. The equivalent cir-

cuit is a 2200pF capacitor charged to 311V connected

through less than 0.1Ω to a signal pin. The MAX4397 is

soldered on the PC board when it experiences such a

discharge. Therefore, the current spike flows through

the ESD protection diodes and is absorbed by the sup-

ply bypass capacitors, which have high capacitance

and low ESR.

To better protect the MAX4397 against excess voltages

during the cable discharge condition, place an addi-

tional 75Ω resistor in series with all inputs and outputs

to the SCART connector. For harsh environments where

±15kV protection is needed, the MAX4385E and

MAX4386E single and quad high-speed op amps fea-

ture the industry’s first integrated ±15kV ESD protection

on video inputs and outputs.

MAX4397

Audio/Video Switch for Dual SCART Connectors

______________________________________________________________________________________ 17

µC

SCL

SDA

VID

MAX4397

SCL

SDA

SCL

SDA

DEVICE 2

DEVICE 1

SDA

Figure 7. Typical I

C Interface Application

ADDRESS PIN

STATE

WRITE

ADDRESS

READ ADDRESS

VID

96h 97h

GNDVID 94h 95h

Table 2. Slave Address Programming

Slave Address

(Write address)

Address

Data

Write Mode

Slave

Address

(Write

address)

Address

Slave

Address

(Read

address)

Data

Read Mode

S = Start Condition, A = Acknowledge, NA = Not Acknowledge,

Sr = Repeat Start Condition, P = Stop Condition

MAX4397

Power Supplies and Bypassing

The MAX4397 features single 5V and 12V supply opera-

tion and requires no negative supply. The +12V supply

is for the SCART switching function. For pin V

place all bypass capacitors as close as possible with a

10µF capacitor in parallel with a 0.1µF ceramic capacitor.

Connect all V

AUD

pins together to +5V and bypass with a

10µF electrolytic capacitor in parallel with a 0.47µF low-

ESR ceramic capacitor to audio ground. Bypass V

AUD

pins with a 0.1µF capacitor to audio ground. Bypass

AUD_BIAS to audio ground with a 10µF electrolytic in

parallel with a 0.1µF ceramic capacitor.

Bypass V

DIG

with a 0.1µF ceramic capacitor to digital

ground. Bypass each V

VID

to video ground with a 0.1µF

ceramic capacitor. Connect V

VID

in series with a 200nH

ferrite bead to the +5V supply.

Layout and Grounding

For optimal performance, use controlled-impedance

traces for video signal paths and place input termina-

tion resistors and output back-termination resistors

close to the MAX4397. Avoid routing video traces par-

allel to high-speed data lines.

The MAX4397 provides separate ground connections

for video, audio, and digital supplies. For best perfor-

mance, use separate ground planes for each of the

ground returns and connect all three ground planes

together at a single point. Refer to the MAX4397 evalu-

ation kit for a proven circuit board layout example.

Audio/Video Switch for Dual SCART Connectors

18 ______________________________________________________________________________________

ADDRESS

(HEXADECIMAL)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2

BIT 1

BIT 0

00h

TV volume

bypass

ZCD TV volume control

TV audio

output mute

01h VCR volume control Not used

Not used

VCR audio selection TV audio selection

02h Not used

03h Not used

04h Not used

05h Not used

06h

TV_R/C_IN

clamp

RGB gain

TV G and B video switch

TV video switch

07h

Not used

RF_CVBS_

OUT switch

TV_Y/

CVBS_OUT switch

TV fast blank

(fast switching)

TV_R/C_OUT

ground

Set function TV

08h

VCR_R/

C_IN clamp

Not used

ENC_R/

C_IN clamp

VCR video switch

09h

Not used Not used

Not used

Not used Not used

VCR_R/C_OUT

ground

Set function VCR

0Ah Not used

0Bh Not used

0Ch Not used

0Dh

VCR_Y/

CVBS_OUT

enable

VCR_R/

C_OUT

enable

TV_R/C_OUT

enable

TV_G_OUT

enable

TV_B_OUT

enable

TV_Y/

CVBS_OUT

enable

TVOUT

_FS

enable

RF_CVBS_

OUT

enable

Table 3. Data Format for Write Mode

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

MAX4397SCTM+T

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Buy MAX4397SCTM+T

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Maxim Integrated

Description:

IC SW A/V SCART CON 48-TQFN

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MAX4397SCTM+T

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