ZL38012 Data Sheet
4
Zarlink Semiconductor Inc.
4.0 PCM / I
2
S Ports
The PCM port supports data communication between an external peripheral device and the ZL38012 DSP Core
using separate input (PCMi) and output (PCMo) serial streams with TDM (i.e., ST-BUS, GCI or McBSP) or SSI
interface timing in both master or slave timing modes.
PCM Port pin functions are shared with the I
2
S Port pin functions. The I
2
S (Inter-IC Sound) port and PCM Port
share the same physical pins of the ZL38012. Selection of either I
2
S port operation or PCM Port operation is done
through the Port PCM/I
2
S Select Register. See firmware manual.
The I
2
S port can be used to connect external Analog-to-Digital Converters or CODECs to the internal DSP. This
port can operate in master mode, where the ZL38012 is the source of the port clocks, or slave mode, where the bit
and sampling clocks (I
2
S_SCK and I
2
S_ LRCK) are inputs to the ZL38012. In I
2
S port master mode the clock signal
at output pin I
2
S_LRCK is the sampling frequency (f
S
), the clock signal at output I
2
S_SCK is 32 x f
S
, and the clock
signal at output I
2
S_MCLK is 256 x f
S
. In I
2
S port slave mode the relationship between the clock signal at input pin
I
2
S_LRCK and the clock signal at input I
2
S_SCK must be 32 x f
S
. In slave mode the 256 x f
S
relationship between
f
S
and the I
2
S_MCLK is not mandatory, and the I
2
S_MCLK output pin will be in a high impedance state.
Access to the control and status registers associated with these ports is through the Slave SPI port or UART.
5.0 Host Microprocessor and Peripheral Interfaces
The ZL38012 provides 1 master SPI port (with 2 chip selects), 1 slave SPI ports and an UART. The master SPI
port’s primary function is to access and external FLASH memory to download firmware to the ZL38012.
The control/status registers and memory of the ZL38012 can be accessed (R/W) by an external host through the
Slave SPI and the UART ports. Register/Memory read and write accesses are carried out through a series of port
read and write accesses as follows:
5.1 Master SPI (FLASH Port)
The Master SPI port is used by the ZL38012 to access one or two peripheral devices (chip select signals
SPIM_CS[1:0]). It supports both SPI and MICROWIRE modes of operation and can write up to 40 bits or read up to
32 bits in a single access. The Chip Select output signals may be programmed for a single access or burst access.
All communication is MSB first and all pins of the master SPI port are outputs controlled by the ZL38012, except
SPIM_MISO.
5.2 Slave SPI (Host Port)
The slave SPI port may be used by an external host microprocessor to access (Read/Write) the ZL38012 internal
control/status registers and memory. Access is initiated when the external host makes signal SPIS_CS
low and is
ended when this signal goes high. The host will then apply a clock (maximum 25 MHz) to signal SPIS_CLK to clock
data out of SPIS_MISO and in on SPIS_MOSI.
