7
AC Timing Characteristics over Temperature Range (-40 to +85°C)
Timing
Diagram 4.5 V<V
LOGIC
< 5.5 V V
LOGIC
= 3 V
Ref. Number Description Symbol Min. Max. Min. Max. Units
1 Register Select Setup Time to Chip Enable t
rss
10 10 ns
2 Register Select Hold Time to Chip Enable t
rsh
10 10 ns
3 Rising Clock Edge to Falling Chip Enable Edge t
clkce
20 20 ns
4 Chip Enable Setup Time to Rising Clock Edge t
ces
35 55 ns
5 Chip Enable Hold Time to Rising Clock Edge t
ceh
20 20 ns
6 Data Setup Time to Rising Clock Edge t
ds
10 10 ns
7 Data Hold Time after Rising Clock Edge t
dh
10 10 ns
8 Rising Clock Edge to D
OUT
[1]
t
dout
10 40 10 65 ns
9 Propagation Delay D
IN
to D
OUT
Simultaneous Mode for one IC
[1,2]
t
doutp
18 30 ns
10 CE Falling Edge to D
OUT
Valid t
cedo
25 45 ns
11 Clock High Time t
clkh
80 100 ns
12 Clock Low Time t
clkl
80 100 ns
Reset Low Time t
rstl
50 50 ns
Clock Frequency F
cyc
5 4 MHz
Internal Display Oscillator Frequency F
inosc
80 210 80 210 KHz
Internal Refresh Frequency F
rf
150 410 150 410 Hz
External Display Oscillator Frequency F
exosc
Prescaler = 1 51.2 1000 51.2 1000 KHz
Prescaler = 8 410 8000 410 8000 KHz
Notes:
1. Timing specications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
8
Display Overview
The HCMS-39XX series is a family of LED displays driven
by on-board CMOS ICs. The LEDs are congured as 5x7
font characters and are driven in groups of 4 characters
per IC. Each IC consists of a 160-bit shift register (the Dot
Register), two 7-bit Control Words, and refresh circuitry.
The Dot Register contents are mapped on a one-to-one
basis to the display. Thus, an individual Dot Register bit
uniquely controls a single LED.
Eight-character displays have two ICs that are cascaded.
The Data Out line of the rst IC is internally connected to
the Data In line of the second IC forming a 320-bit Dot
Register. The display’s other control and power lines are
connected directly to both ICs.
Reset
Reset initializes the Control Registers (sets all Control
Register bits to logic low) and places the display in the
sleep mode. The Reset pin should be connected to the
system power on reset circuit. The Dot Registers are not
cleared upon power-on or by Reset. After power-on,
the Dot Register contents are random; however, Reset
will put the display in sleep mode, thereby blanking the
LEDs. The Control Register and the Control Words are
cleared to all zeros by Reset.
To operate the display after being Reset, load the Dot
Register with logic lows. Then load Control Word 0 with
the desired brightness level and set the sleep mode bit
to logic high.
Dot Register
The Dot Register holds the pattern to be displayed by the
LEDs. Data is loaded into the Dot Register according to
the procedure shown in Table 1 and Figure 5.
First RS is brought low, then CE is brought low. Next, each
successive rising CLK edge will shift in the data at the D
IN
pin. Loading a logic high will turn the corresponding
LED on; a logic low turns the LED o. When all 160 bits
have been loaded (or 320 bits in an 8-digit display), CE is
brought to logic high.
When CLK is next brought to logic low, new data is
latched into the display dot drivers. Loading data into
the Dot Register takes place while the previous data is
displayed and eliminates the need to blank the display
while loading data.
Table 1. Register Truth Table
Function CLK CE RS
Select Dot Register Not Rising p L
Load Dot Register n L X
D
IN
= HIGH LED = “ON”
D
IN
= LOW LED = “OFF”
Copy Data from Dot Register to Dot Latch L H X
Select Control Register Not Rising p H
Load Control Register
[1,3]
n L X
Latch Data to Control Word
[2]
L H X
Notes:
1. BIT D
0
of Control Word 1 must have been previously set to Low for serial mode or High for simultaneous mode.
2. Selection of Control Word 1 or Control Word 0 is set by D
7
of the Control Shift Register. The unselected control word retains its previous value.
3. Control Word data is loaded Most Signicant Bit (D
7
) rst.
9
Figure 5. HCMS-39XX write cycle timing diagram
Pixel Map
In a 4-character display, the 160-bits are arranged as 20
columns by 8 rows. This array can be conceptualized as
four 5 x 8 dot matrix character locations, but only 7 of
the 8 rows have LEDs (see Figures 6 & 7). The bottom
row (row 0) is not used. Thus, latch location 0 is never
displayed. Column 0 controls the left-most column.
Data from Dot Latch locations 0-7 determine whether
or not pixels in Column 0 are turned-on or turned-o.
Therefore, the lower left pixel is turned-on when a logic
high is stored in Dot Latch location 1. Characters are
loaded in serially, with the left-most character being
loaded rst and the right-most character being loaded
last. By loading one character at a time and latching
the data before loading the next character, the gures
will appear to scroll from right to left.
NOTE:
1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
T
RSS
RSH
T
T
CLKCE CES
T
CLKH
T
CLKL
T
CEH
T
DS
T
DH
T
CEDO
T
DOUT
T
DOUTP
T
PREVIOUS DATA NEW DATA
NEW DATA LATCHED HERE
[1]
CE
RS
CLK
D
IN
LED OUTPUTS,
CONTROL
REGISTERS
D
OUT
S
IMULTANEOUS)
D
OUT
(SERIAL)
3
4
12
5
12
11
6
7
10
8
9

HCMS-3913

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
LED Displays & Accessories Green 574nm 1x8 Alphanumeric
Lifecycle:
New from this manufacturer.
Delivery:
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