FS7140, FS7145
http://onsemi.com
6
Table 6. SERIAL INTERFACE TIMING SPECIFICATIONS (Note 3)
Parameter
Symbol Conditions/Description
Fast Mode
Units
Min Max
Clock frequency f
SCL
SCL 0 400 kHz
Bus free time between STOP and START t
BUF
1300 ns
Set−up time, START (repeated) T
su:STA
600 ns
Hold time, START t
hd:STA
600 ns
Set−up time, data input T
su:DAT
SDA 100 ns
Hold time, data input t
hd:DAT
SDA 0 ns
Output data valid from clock t
AA
900 ns
Rise time, data and clock t
R
SDA, SCL 300 ns
Fall time, data and clock t
F
SDA, SCL 300 ns
High time, clock t
HI
SCL 600 ns
Low time, clock t
LO
SCL 1300 ns
Set−up time, STOP t
su:STO
600 ns
3. Unless otherwise stated, V
DD
= 3.3 V ± 10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are ± 3s from typical.
FUNCTIONAL BLOCK DIAGRAM
Phase Locked Loop (PLL)
The PLL is a standard phase− and frequency−locked loop
architecture. The PLL consists of a reference divider, a
phase−frequency detector (PFD), a charge pump, an internal
loop filter, a voltage−controlled oscillator (VCO), a
feedback divider, and a post divider.
The reference frequency (generated by either the
on−board crystal oscillator or an external frequency source),
is first reduced by the reference divider. The integer value
that the frequency is divided by is called the modulus and is
denoted as NR for the reference divider. This divided
reference is then fed into the PFD.
The VCO frequency is fed back to the PFD through the
feedback divider (the modulus is denoted by NF).
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal. The
input/output relationship between the reference frequency
and the VCO frequency is then:
f
VCO
N
F
+
f
REF
N
R
This basic PLL equation can be rewritten as
f
VCO
+ f
REF
ǒ
N
F
N
R
Ǔ
A post divider (actually a series combination of three post
dividers) follows the PLL and the final equation for device
output frequency is:
f
CLK
+ f
REF
ǒ
N
F
N
R
Ǔǒ
1
N
Px
Ǔ
Reference Divider
The reference divider is designed for low phase jitter. The
divider accepts the output of either the crystal oscillator
circuit or an external reference frequency. The reference
divider is a 12 bit divider, and can be programmed for any
modulus from 1 to 4095 (divide by 1 not available on date
codes prior to 0108).
Feedback Divider
The feedback divider is based on a dual−modulus divider
(also called dual−modulus prescaler) technique. It permits
division by any integer value between 12 and 16383. Simply
program the FBKDIV register with the binary equivalent of
the desired modulus. Selected moduli below 12 are also
permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4
and 5 are not available on date codes prior to 0108).
Post Divider
The post divider consists of three individually
programmable dividers, as shown in Figure 2.
