FS7140, FS7145
http://onsemi.com
13
Table 9. DEVICE CONFIGURATION BITS
Name Description
REFDSRC
Reference divider source
[0] = crystal oscillator / [1] = REF pin
FBKDSRC
Feedback divider source
[0] = VCO output / [1] = post divider output
SHUT1
Shutdown1
[0] = normal / [1] = powered down
SHUT2
Shutdown2
[0] = normal / [1] = powered down
CMOS
CLKP/CLKN output mode
[0] = PECL output / [1] CMOS output
Table 10. MAIN LOOP TUNING BITS
Name Description
CP[1:0]
Charge pump current
[00]
2.0 mA
[01]
4.5 mA
[10]
11.0 mA
[11]
22.5 mA
LR[1:0]
Loop filter resistor select
[00]
400 KW
[01]
133 KW
[10]
30 KW
[11]
12 KW
LC
Loop filter capacitor select
[0] 185 pF
[1] 500 pF
Table 11. PLL DIVIDER CONTROL BITS
Name Description
REFDIV[11:0] Reference divider (N
R
)
FBKDIV[13:0] Feedback divider (N
R
)
Table 12. SYNC CONTROL BITS (FS7145 only)
Name Description
SYNCEN
Sync enable
[0] = disabled / [1] = enabled
SYNCPOL
Sync polarity
[0] = negative edge / [1] = positive edge
Table 13. POST DIVIDER CONTROL BITS
Name Description
POST1[3:0]
Post divider #1 (N
P1
) modulus
[0000] 1
[0001] 2
[0010] 3
[0011] 4
[0100] 5
[0101] 6
[0110] 7
[0111] 8
[1000] 9
[1001] 10
[1010] 11
[1011] 12
[1100]
Do not use
[1101]
[1110]
[1111]
POST2[3:0]
Post divider #2 (N
P2
) modulus
[0000] 1
[0001] 2
[0010] 3
[0011] 4
[0100] 5
[0101] 6
[0110] 7
[0111] 8
[1000] 9
[1001] 10
[1010] 11
[1011] 12
[1100]
Do not use
[1101]
[1110]
[1111]
POST3[1:0]
Post divider #3 (N
P3
) modulus
[00] 1
[01] 2
[10] 4
[11] 8
