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74LVCH32245AEC,551

P1-P3P4-P6P7-P9P10-P12P13-P15
74LVCH32245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 15 December 2011 7 of 15
NXP Semiconductors
74LVCH32245A
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
[1] All typical values are measured at V
CC
= 3.3 V and T
amb
=25C.
[2] The bus hold circuit is switched off when V
I
>V
CC
allowing 5.5 V on the input pin.
[3] Valid for data inputs only. Control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified V
I
level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristics
I
BHL
bus hold
LOW current
V
CC
= 1.65; V
I
= 0.58 V
[3][4]
10 - - 10 - A
V
CC
= 2.3; V
I
= 0.7 V 30 - - 25 - A
V
CC
= 3.0; V
I
= 0.8 V 75 - - 60 - A
I
BHH
bus hold
HIGH
current
V
CC
= 1.65; V
I
= 1.07 V
[3][4]
10 - - 10 - A
V
CC
= 2.3; V
I
= 1.7 V 30 - - 25 - A
V
CC
= 3.0; V
I
= 2.0 V 75 - - 60 - A
I
BHLO
bus hold
LOW
overdrive
current
V
CC
= 1.95 V
[3][5]
200 - - 200 - A
V
CC
= 2.7 V 300 - - 300 - A
V
CC
= 3.6 V 500 - - 500 - A
I
BHHO
bus hold
HIGH
overdrive
current
V
CC
= 1.95 V
[3][5]
200 - - 200 - A
V
CC
= 2.7 V 300 - - 300 - A
V
CC
= 3.6 V 500 - - 500 - A
Table 6. Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6
.
Symbol Parameter Conditions T
amb
= 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation
delay
nAn to nBn; nBn to nAn; see Figure 4
[2]
V
CC
= 1.2 V - 13.0 - - - ns
V
CC
= 1.65 V to 1.95 V 1.5 5.2 12.2 1.5 13.8 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.8 6.0 1.0 6.7 ns
V
CC
= 2.7 V 1.0 2.7 4.7 1.0 6.0 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.4 4.5 1.0 6.0 ns
t
en
enable time nOE to nAn, nBn: see Figure 5
[2]
V
CC
= 1.2 V - 15.0 - - - ns
V
CC
= 1.65 V to 1.95 V 1.5 5.9 15.0 1.5 16.9 ns
V
CC
= 2.3 V to 2.7 V 1.0 3.3 7.9 1.0 8.8 ns
V
CC
= 2.7 V 1.5 3.5 6.7 1.5 8.5 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.7 5.5 1.0 7.0 ns
74LVCH32245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 15 December 2011 8 of 15
NXP Semiconductors
74LVCH32245A
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2, 1.8, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
t
en
is the same as t
PZL
and t
PZH
.
t
dis
is the same as t
PLZ
and t
PHZ
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs.
11. Waveforms
t
dis
disable time nOE to nAn, nBn; see Figure 5
[2]
V
CC
= 1.2 V - 11.0 - - - ns
V
CC
= 1.65 V to 1.95 V 1.5 4.9 13.1 1.5 14.7 ns
V
CC
= 2.3 V to 2.7 V 0.5 2.7 7.1 0.5 7.9 ns
V
CC
= 2.7 V 1.5 3.4 6.6 1.5 8.5 ns
V
CC
= 3.0 V to 3.6 V 1.5 3.3 5.6 1.5 7.0 ns
t
sk(o)
output skew
time
V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power
dissipation
capacitance
per buffer; V
I
=GNDtoV
CC
[4]
V
CC
= 1.65 V to 1.95 V - 11.5 - - - pF
V
CC
= 2.3 V to 2.7 V - 15.2 - - - pF
V
CC
= 3.0 V to 3.6 V - 18.5 - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.
Symbol Parameter Conditions T
amb
= 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
V
M
= 1.5 V at V
CC
2.7 V.
V
M
=0.5 V
CC
at V
CC
<2.7V.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 4. The input (nAn, nBn) to output (nBn, nAn) propagation delays
mna477
nAn, nBn
input
nBn, nAn
output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
OH
V
OL
74LVCH32245A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 15 December 2011 9 of 15
NXP Semiconductors
74LVCH32245A
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
V
M
= 1.5 V at V
CC
2.7 V.
V
M
=0.5 V
CC
at V
CC
<2.7V.
V
X
= V
OL
+ 0.3 V at V
CC
2.7 V;
V
X
= V
OL
+ 0.15 V at V
CC
2.7 V.
V
Y
= V
OH
0.3 V at V
CC
2.7 V;
V
Y
= V
OH
0.15 V at V
CC
2.7 V.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 5. 3-state enable and disable times.
mna362
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
P1-P3P4-P6P7-P9P10-P12P13-P15

74LVCH32245AEC,551

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Buy 74LVCH32245AEC,551
Manufacturer:
NXP Semiconductors
Description:
IC TXRX NON-INVERT 3.6V 96LFBGA 74LVCH
Lifecycle:
New from this manufacturer.
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