NCV7703B
http://onsemi.com
13
H−Bridge Driver Configuration
The NCV7703B has the flexibility of controlling each half
bridge driver independently. This allows for high side, low
side and H−bridge control. H−bridge control provides
forward, reverse, brake and high impedance states.
Overvoltage Clamping − Driving Inductive Loads
Each output is internally clamped to ground and Vs by
internal free wheeling diodes. The diodes have ratings that
complement the FETs they protect.
Overcurrent Shutdown Threshold Detection (Table 2)
The state of input bit 13 (OCD) selects driver reaction
when reaching overcurrent shutdown threshold. With a “0”
for input bit 13, the OLD status bit will be set to “1” when
the level exceeds the overcurrent shutdown shut−down
threshold and the driver will remain on. With a “1” for input
bit 13, the output driver shuts off when the overcurrent
shutdown threshold is exceeded and can only be turned back
on via the SPI port with a SPI command that includes an SRR
= 1. Note: high currents could cause a high rise in die
temperature. Devices will not be allowed to turn on if the die
temperature exceeds the thermal shutdown temperature.
Current Limit Fault
The current limit fault circuit will shut down the offending
output driver when the Current Limit (Source or Sink) has
been exceeded for a duration greater than 200 ms, regardless
of the OLD input bit status. The OUTx output bit will report
a “0” indicating which driver encountered the hard short.
The OLD status bit will be set and will remain set until a new
SRR input SPI command is executed.
Under−Load Detection (Table 3)
The under−load detection circuit monitors the current
from each output driver. A minimum load current (this is the
maximum open circuit detection threshold) is required when
the drivers are turned on. If the under−load detection
threshold has been detected for more than the under−load
delay time, the ULD bit (output bit #14) will be set to a “1”.
The under load bit is reset with SRR.
Overvoltage Shutdown (Table 4)
Overvoltage lockout circuitry monitors the voltage on the
V
S
pin. The response to an overvoltage condition is selected
by SPI input bit 15. PSF output bit 15 is set when a V
S
overvoltage condition exists. If input bit 15 (OVLO) is set
to “1”, all outputs will turn off during this overvoltage
condition. Turn On/Off status is maintained in the logic
circuitry, so that when proper input voltage level is
reestablished, the programmed outputs will turn back on.
The PSF output bit is reset with SRR.
Table 2. INPUT BIT 13, OVERCURRENT DETECTION SHUT DOWN CONTROL AND RESPONSE
OLD Input
Bit 13 Set
Typical Load Current
Condition
Output Bit 13 OLD Status OUTx Status
0 I
L
≤ 1.4 A 0 Unchanged
0 1.4 A < I
L
≤ 3 A 1 (Need SRR to reset) Unchanged
0
I
L
≥ 3 A, for 200 ms (typ)
1 (Need SRR to reset) OUTx Latched Off (Need SRR to reset)
1 I
L
≤ 1.4 A 0 Unchanged
1
I
L
> 1.4 A, for 25 ms (typ)
1 (Need SRR to reset) OUTx Latched Off (Need SRR to reset)
Table 3. OUTPUT BIT 14, UNDER LOAD DETECTION SHUT DOWN
OUTx ULD Set Output Data Bit 14, Under Load Detect (ULD) Status OUTx Status
0 0 Unchanged
1 1 (Need SRR to reset) Unchanged
Table 4. INPUT BIT 15, OVERVOLTAGE LOCK OUT (OVLO) SHUT DOWN
OVLO Input
Bit 15
V
S
OVLO
Condition
Output Data Bit 15 Power
Supply Fail (PSF) Status
OUTx Status
0 0 0 Unchanged
0 1 1 (Need SRR to reset) Unchanged
1 0 0 Unchanged
1 1 1 (Need SRR to reset) All Outputs Shut Off (Remain off until V
S
is out of OVLO)
