MC74HC597A
http://onsemi.com
5
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
V
CC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C v 125_C
f
max
Maximum Clock Frequency (50% Duty Cycle), Shift Clock
(Figures 4 and 10)
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Clock to Q
H
(Figures 3 and 10)
2.0
3.0
4.5
6.0
175
100
40
30
225
110
50
40
275
125
60
50
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Shift Clock to Q
H
(Figures 4 and 10)
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
t
PHL
Maximum Propagation Delay, Reset to Q
H
(Figures 5 and 10)
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Serial Shift/Parallel Load to Q
H
(Figures 6 and 10)
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 3 and 10)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance — 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
40
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
S
A
(Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load
is high. Data on this input is ignored
when Serial Shift/Parallel Load
is low.
CONTROL INPUTS
Serial Shift/Parallel Load
(Pin 13)
Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
Reset (Pin 10)
Asynchronous, Active−low shift register reset. A low level
applied to this input resets the shift register to a low level,
but does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A low−to−high transition on this
input shifts data on the Serial Data Input into the shift
register and data in stage H is shifted out Q
H
, being
replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
Latch clock. A low−to−high transition on this input loads
the parallel data on inputs A−H into the input latch.
OUTPUT
Q
H
(Pin 9)
Serial data output. This pin is the output from the last
stage of the shift register.
