MC74HC597ADR2G

MC74HC597A
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7
FUNCTION TABLE
Operation
Inputs Resulting Function
Reset
Serial Shift/
Parallel Load
Latch
Clock
Shift
Clock
Serial
Input
S
A
Parallel
Inputs
AH
Latch
Contents
Shift
Register
Contents
Output
Q
H
Reset shift register L X L, H, X X X U L L
Reset shift register; load
parallel data into data latch
L X X X ah ah L L
Load parallel data into data
latch
H H L,H, X ah ah U U
Transfer latch contents to
shift register
H L L, H, X X X U LR
N
SR
N
LR
H
Contents of data latch and
shift register are
unchanged
H H L, H, L,H, X X U U U
Load parallel data into data
latch and shift register
H L X X ah ah ah h
Shift serial data into shift
register
H H X D X * SR
A
= D;
SR
N
SR
N+1
SR
G
SR
H
Load parallel data into data
latch and shift serial data
into shift register
H H D ah ah SR
A
= D;
SR
N
SR
N+1
SR
G
SR
H
LR = latch register contents ah = data at parallel data inputs AH U = remains unchanged
SR = shift register contents D = data (L, H) at serial data input S
A
X = don’t care
* = depends on latch clock input
MC74HC597A
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8
SWITCHING WAVEFORMS
SERIAL SHIFT/
PARALLEL LOAD
Q
H
50%
t
PLH
50%
V
CC
GND
t
PHL
50%
t
w
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
50%
50%
RESET
Q
H
SHIFT CLOCK
t
PHL
t
rec
V
CC
GND
SERIAL SHIFT/
PARALLEL LOAD
SHIFT CLOCK
50%
50%
t
su
V
CC
GND
V
CC
GND
t
w
LATCH CLOCK
Q
H
t
r
t
f
V
CC
GND
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
SHIFT CLOCK
Q
H
V
CC
GND
50%
50%
t
PLH
t
PHL
1/f
max
90%
50%
10%
t
w
50%LATCH CLOCK
V
CC
VALID
GND
V
CC
GND
t
su
t
h
50%
PARALLEL DATA
A/H
50%SHIFT CLOCK
V
CC
VALID
GND
V
CC
GND
t
su
t
h
50%
SERIAL DATA
INPUT S
A
t
w
Figure 3. (Serial Shift/Parallel Load = L) Figure 4. (Serial Shift/Parallel Load = H)
Figure 5. Figure 6.
Figure 7. Figure 8.
Figure 9. Figure 10. Test Circuit
MC74HC597A
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9
PARALLEL
DATA
INPUTS
14
11
13
12
15
1
2
3
4
5
6
7
SERIAL DATA
INPUT, S
A
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
A
B
C
D
E
F
G
H
STAGE A
STAGE B
STAGE C*
STAGE D*
STAGE E*
STAGE F*
STAGE G*
STAGE H
D
C
Q
D
C
Q
D
CQ
S
R
D
CQ
S
R
D
C
Q
D
CQ
S
R
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
EXPANDED LOGIC DIAGRAM
9
Q
H
10
RESET
Figure 11. Extended Logic Diagram

MC74HC597ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers IC SHIFT REGISTER 8-BIT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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