OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

IS42RM16800G-6BLI-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
10
www.issi.com - DRAM@issi.com
Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of
output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is
m
clocks, the data will be available by clock edge
n +
m. The DQs will start driving as a result of the clock edge one cycle earlier
(n + m
-
1), and provided that the relevant access times are met, the data will be valid by clock edge
n +
m. For example, assuming that the
clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to
two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
CLK
COMMAND
DQ
NOP NOP
Dout
T0 T1 T2
tLZ
tOH
tAC
CAS Latency=2
T3
READ
CLK
COMMAND
DQ
NOP NOP
Dout
T0 T1 T2
tLZ
tOH
tAC
CAS Latency=3
T3
NOP
T4
READ
DON’T CARE
UNDEFINED
Figure6: CAS Latency
11
www.issi.com - DRAM@issi.com
Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
Table4: Command Truth Table
Function CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR A10 Note
Command Inhinit (NOP) H X H X X X X X
No Operation (NOP) H X L H H H X X
Mode Register Set H X L L L L X OP CODE 4
Extended Mode Register Set H X L L L L X OP CODE 4
Active (select bank and
activate row)
H X L L H H X Bank/Row
Read H X L H L H L/H Bank/Col L 5
Read with Autoprecharge H X L H L H L/H Bank/Col H 5
Write H X L H L L L/H Bank/Col L 5
Write with Autoprecharge H X L H L L L/H Bank/Col
H 5
Precharge All Banks H X L L H L X X H
Precharge Selected Bank H X L L H L X Bank L
Burst Stop H H L H H L X X
Auto Refresh H H L L L H X X 3
Self Refresh Entry H L L L L H X X 3
Self Refresh Exit L H
H X X X
X X 2
L H H H
Precharge Power Down Entry H L
H X X X
X X
L H H H
Precharge Down Exit L H
H X X X
X X
L H H H
Clock Suspend Entry H L
H X X X
X X
L V V V
Clock Suspend Exit L H X X X
Deep Power Down Entry H L L H H L X X 6
Deep Power Down Exit L H X X X
Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
H: High Level, L: Low Level, X: Don't Care, V: Valid
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A11 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended
mode register set.
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
DQM Latency is 2 CLK.
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
assigned to the Deep Power Down function.
12
www.issi.com - DRAM@issi.com
Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
Table5: Function Truth Table
Current
State
Command
Action Note
/CS /RAS /CAS /WE BA A0-A11 Description
Idle
L L L L OP CODE Mode Register Set Set the Mode Register 14
L L L H X X Auto or Self Refresh
Start Auto or Self
Refresh
5
L L H L BA X Precharge No Operation
L L H H BA Row Add. Bank Activate
Activate the Specified
Bank and Row
L H L L BA Col Add./ A10 Write/WriteAP ILLEGAL 4
L H L H BA Col Add./ A10 Read/ReadAP ILLEGAL 4
L H H H X X No Operation No Operation 3
H X X X X X Device Deselect
No Operation or Power
Down
3
Row
Active
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge Precharge 7
L L H H BA Row Add. Bank Activate ILLEGAL 4
L H L L BA Col Add./A10 Write/Write AP
Start Write : Optional
AP(A10=H)
6
L H L H BA Col Add./A10 Read/Read AP
Start Read : Optional
AP(A10=H)
6
L H H H X X No Operation No Operation
H X X X X X Device Deselect No Operation
Read
L L L L OP CODE Mode Register Set ILLEGAL 13,14
L L L H X X Auto or Self Refresh ILLEGAL 13
L L H L BA X Precharge
Termination Burst :
Start the Precharge
L L H H BA Row Add. Bank Activate ILLEGAL 4
L H L L BA Col Add./A10 Write/WriteAP
Termination Burst :
Start Write(AP)
8,9
L H L
H BA Col Add./A10 Read/Read AP
Terimination Burst :
Start Read(AP)
8
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

IS42RM16800G-6BLI-TR

Mfr. #:
Buy IS42RM16800G-6BLI-TR
Manufacturer:
Description:
IC DRAM 128M PARALLEL 54TFBGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet